LTC6955 datasheet(15/22 Pages) AD

15 / 22 page

LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Supply Bypassing and PCB Layout Guidelines

Care must be taken when creating a PCB layout to mini-

mize power supply decoupling and ground inductances.

All power supply V+ pins should be bypassed directly to

the ground plane using either a 0.01µF or a 0.1µF ceramic

capacitor as called out in the Pin Functions section as

close to the pin as possible. Multiple vias to the ground

plane should be used for all ground connections, includ-

ing to the power supply decoupling capacitors.

The presence of the divide-by-2 output on the LTC6955-1

causes a spur to appear on the other buffered outputs of

the part. This spur can be improved by adding a ferrite

bead in series with the VOUT+ supply pin for OUT10 (Pin 6).

See the Typical Application Generation of 7.25GHz, 52fs

ADC SNR Jitter Clocks Using LTC6952 and LTC6955-1

for an example.

The package’s exposed pad is a ground connection, and

must be soldered directly to the PCB land. The PCB land

pattern should have multiple thermal vias to the ground

plane for both low ground inductance and also low ther-

mal resistance (see Figure 5 for an example). An example

of grounding for electrical and thermal performance can

be found on the DC2611 layout.

Figure 5. PCB Top Metal Layer Pin and Exposed Ground Pad

Design. Pin 41 Is Signal Ground and Connected Directly to the

Exposed Pad Metal

6955 F05

LTC6955 Datasheet(PDF) 15 Page - Analog Devices