UBA2074(A)

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 02.0 — February 2007

23 of 33

NXP Semiconductors

UBA2074(A)

High Voltage Full-bridge control IC for CCFL backlighting

[1]

The zener clamp on pin VDD is only activated for high start-up level (

[2]

GLA, GLB, GHA and GHB open.

[3]

each cyle low and the lamps are 20% of the time on, resulting in een light output of 20%.

11. Application information

Figure 20 shows an example backlighting configuration, where the inverter is supplied by

a high voltage (for instance 400V) and the IC is supplied via a start-up bleeder resistor

and a dV/dt supply. Two lamp are connected, each to another output of the same

transformer. The leakage inductances of this transformer provides the ballast impedances

for the lamp. Inductors L1 and L2 provide current for zero voltage switching during PWM

dimming. An analogue voltage is converted to a PWM signal to provide for the desired

brightness level PWM signal. Synchronisation to a predetermined frequency can also be

achieved, when required. Optional lamp short detection is via the lamp voltage sensing

and D13, D23 and the nonFAULT-pin is indicated.

maximum low output current on

pin nonFAULT

0.75

1

1.5

mA

Chip enable levels

logic high level on pin EN

1.7

V

logic low level on pin EN

0.9

V

Synchronisation

amplitude of input pulse on pin

SYNC

2.5

5

V

input pulse width at SYNC pin

0.3

µs

input pulse duty cycle at SYNC

pin

50

%

input sync frequency

1

1.1

amplitude of output pulse of pin

SYNC

load on SYNC pin 4.7k

Ω//10pF

2.5

2.9

3.3

V

Output pulse width of SYNC

pin

load on SYNC pin 4.7k

Ω//10pF

0.36

0.44

0.52

µs

Table 5:

to a capacitor, unless otherwise specified. All voltages are measured with respect to signal ground (pin 7); currents are

positive when flowing into the IC.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit