November 22, 2004

15

Philips Semiconductors

Preliminary specification

Universal LCD driver

for low multiplex rates

PCF8562

6.5

Oscillator

6.5.1

The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external

guarantee that the clock starts.

6.5.2

A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state.

6.6

Timing

The PCF8562 timing controls the internal data flow of the device. This includes the transfer of display data from the

display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived

from the clock frequency. The frame signal frequency is a fixed division integer of the clock frequency (nominally 64 kHz)

from either the internal or an external clock.

Frame frequency =

6.7

Display register

The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one

relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM.

6.8

Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The

segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the

display latch. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit.

6.9

Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The

backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane

outputs are required, the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the same

signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2

multiplex drive mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to

increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

6.10

Display RAM

The display RAM is a static 32

× 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state

of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence

between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane

outputs. The first RAM column corresponds to the 32 segments operated with respect to backplane BP0 (see Fig.10). In

multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance

with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with

the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.

For example, in the 1 : 2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a

f

CLK

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