CPC7595 datasheet(20/25 Pages) IXYS

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INTEGRATED CIRCUITS DIVISION

www.ixysic.com

R03

CPC7595

2.7 Power Supplies

Both a +5 V supply and battery voltage are connected

to the CPC7595. Switch state control is powered

exclusively by the +5 V supply. As a result, the

CPC7595 exhibits extremely low power consumption

during active and idle states.

Although battery power is not used for switch control, it

is required to supply trigger current for the integrated

internal protection circuitry SCR during fault

conditions. This integrated SCR is designed to

activate whenever the voltage at TBAT or RBAT drops 2

to 4 V below the applied voltage on the VBAT pin.

Because the battery supply at this pin is required to

source trigger current during negative overvoltage

fault conditions at tip and ring, it is important that the

net supplying this current be a low impedance path for

high speed transients such as lightning. This will

permit trigger currents to flow enabling the SCR to

activate and thereby prevent a fault induced negative

overvoltage event at the TBAT or RBAT nodes.

2.8 Battery Voltage Monitor

The CPC7595 also uses the VBAT pin to monitor

battery voltage. If the system battery voltage is lost,

the CPC7595 immediately enters the all-off state. It

remains in this state until the system battery voltage is

restored. The device also enters the all-off state if the

battery voltage rises more positive than about –10 V

and remains in the all-off state until the battery voltage

drops below –15 V. This battery monitor feature draws

a small current from the battery (less than 1

A

typical) and will add slightly to the device’s overall

power dissipation.

This monitor function performs properly if the

CPC7595 and SLIC share a common battery supply

origin. Otherwise, if battery is lost to the CPC7595 but

not to the SLIC, the VBAT pin will be internally biased

by the potential applied to the TBAT or RBAT pins via

the internal protection circuitry SCR trigger current

path.

2.9 Protection

2.9.1 Diode Bridge/SCR

The CPC7595 uses a combination of current limited

break switches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient events such as lightning. During a

positive transient condition, the fault current is

conducted through the diode bridge to ground via

FGND. Voltage is clamped to a diode drop above

ground. During a negative transient of 2 to 4 V more

negative than the voltage source at VBAT, the SCR

conducts and faults are shunted to FGND via the SCR

or the diode bridge.

In order for the SCR to crowbar or foldback, the SCR’s

on-voltage (see “Protection Circuitry Electrical

Specifications” on page 13) must be less than the

applied voltage at the VBAT pin. If the VBAT voltage is

less negative than the SCR on-voltage, or if the VBAT

supply is unable to source the trigger current, the SCR

will not crowbar.

For power induction or power-cross fault conditions,

the positive cycle of the transient is clamped to a diode

drop above ground and the fault current is directed to

ground. The negative cycle of the transient will cause

the SCR to conduct when the voltage exceeds the

VBAT reference voltage by two to four volts, steering

the fault current to ground.

Note: The CPC7595xB does not contain a protection

SCR but instead utilizes a diode bridge to clamp both

polarities of a fault transient. These diodes pass the

charge of negative fault potentials to the VBAT pin.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the talk state, the current is passed along the line to

the integrated protection circuitry and restricted by the

dynamic current limit response of the active switches.

During the talk state when a 1000V 10x1000

S pulse

(GR-1089-CORE lightning) is applied to the line

though a properly clamped external protector, the

current seen at TLINE or RLINE will be a pulse with a

typical magnitude of 2.5 A and a duration of less than

0.5

s.

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