AD5930 datasheet(6/28 Pages) AD

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AD5930

Data Sheet

Rev. D | Page 6 of 28

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.

Table 2.1

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments

ns min

MCLK period

ns min

MCLK high duration

ns min

MCLK low duration

ns min

SCLK period

ns min

SCLK high time

ns min

SCLK low time

ns min

FSYNC to SCLK falling edge setup time

ns min

FSYNC to SCLK hold time

ns min

Data setup time

t10

ns min

Data hold time

t11

2 x t1

ns min

Minimum CTRL pulse width

t12

ns min

CTRL rising edge to MCLK falling edge setup time

t13

10 x t1

ns typ

CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)

8 x t1

ns typ

CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)

t14

2 x t1

ns typ

Frequency change to SYNC output, saw sweep, each frequency increment

t15

2 x t1

ns typ

Frequency change to SYNC output, saw sweep, end of sweep

t16

2 x t1

ns typ

Frequency change to SYNC output, triangle sweep, end of sweep

t17

ns max

MCLK falling edge after 16th clock edge to MSB out

1 Guaranteed by design, not production tested.

MCLK

Figure 3. Master Clock

SCLK

FSYNC

SDATA

D15

D14

D15

D14

t10

Figure 4. Serial Timing

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