PE3293 datasheet(2/18 Pages) ETC

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PE3293

Product Specification

 Peregrine Semiconductor Corp. 2003

File No. 70/0015~02C

| UTSi  CMOS RFIC SOLUTIONS

Page 2 of 18

Figure 2. Pin Configuration: TSSOP (JEDEC MO-153-AC)

Table 1. Pin Descriptions

Pin No.

Pin Name

Type

Description

N / C

No connect.

VDD

(Note 1)

Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as

close as possible to this pin and be connected directly to the ground plane.

CP1

Output

Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO.

GND

Ground.

fin1

Input

Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz.

Dec1

Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be

connected directly to the ground plane.

VDD1

PLL1 prescaler power supply. 3.3 kohm resistor to VDD.

Input

Reference frequency input.

GND

Ground.

foLD

Output

Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data

out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table).

Clock

Input

CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift

Data

Input

Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.

Input

Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into

one of the four appropriate latches (as assigned by the control bits).

VDD2

Output

PLL2 prescaler power supply. 3.3 kohm resistor to VDD.

Dec2

Output

Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be

connected directly to the ground plane.

fin2

Input

Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.

GND

Ground.

CP2

Output

Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO.

VDD

(Note 1)

Same as pin 2.

VDD

(Note 1)

Same as pin 2.

Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.

N/C

CP1

GND

in1

Dec1

DD1

GND

oLD

Clock

Data

DD2

DEC2

in2

GND

CP2

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