PE3293 datasheet(12/18 Pages) ETC

Part #	PE3293

Description	1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

PDF	18 Pages

Scroll/Zoom	100%

Manufacturer	ETC [List of Unclassifed Manufacturers]

Direct Link

Logo

12 / 18 page

PE3293

Product Specification

 Peregrine Semiconductor Corp. 2003

File No. 70/0015~02C

| UTSi  CMOS RFIC SOLUTIONS

Page 12 of 18

Phase Comparator Characteristics

PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1

directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to

sink current. If C11 = LOW, UP1 and DOWN1 are interchanged.

PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2

directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to

sink current. If C21 = LOW, UP2 and DOWN2 are interchanged.

Figure 7. Phase Comparator Timing Diagram

Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11.

c1 (2)

(Note 1)

p1 (2)

(Note 1)

LD1 (2)

(Note 1)

UP1 (2)

DOWN1 (2)

c leads fp

c = fp

c lags fp

PE3293 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers