Micrel

MICRF010

June 2005

10

M9999-063005

(408) 955-1690

DO Pin

The output stage for the digital output (DO) is shown in

Figure 4. The output is a 45µA push and 45µA pull

switched-current stage. This output stage is capable of

driving

CMOS

loads.

An

external

buffer-driver

is

recommended for driving high capacitance loads.

VDD

VSS

Compa-

rator

45uA

45uA

DO

Figure 4. DO Pin

REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is quite high (290kΩ). This is a Colpitts

oscillator, with internal 10pF capacitors.

Externally

applied

signals

should

be

AC-coupled,

DC bias voltage on this pin is 1.4V

250

200k

Active

Bias

REFOSC

10pF

10pF

30uA

VDD

VSS

VSS

Figure 5. REFOSC Pin

SHUT Pin

to Interna

Circuits

VDD

VSS

SHUT

Q2

Q3

Q1

VSS

Figure 6. SHUT Pin

Control input circuitry is shown in Figure 6. The standard

input is a logic inverter constructed with minimum geometry

MOSFETs (Q2, Q3). P-Channel MOSFET Q1 is a large

channel length device, which functions essentially as a

“weak” pull-up to VDDBB. Typical pull-up current is 5µA,

leading to an impedance to the VDD supply of typically

1MΩ.