AV2722 (Preliminary)

6-29

January 22, 2004

SC

SFDA

SFAD

SDI

SDO

AV2722

AUDIO

DSP

PROCESSOR

AV2722 in Master Mode

SDI audio data setup time

SDI audio data hold time

SFDA (PIN 4) OR

SFAD (PIN 6)

SC (PIN 2)

SDI (pin 3)

SFDA/SFAD propagation delay from SC

tmsfd

10 ns

10 ns

10 ns

Audio Data Input Timing - MASTER MODE

tmsdod

SDO propagation delay from SC

(min)

(min)

(max)

10 ns

SDO (pin 5)

tmsdod

tmsfd

(max)

MASTER AND SLAVE MODE OPERATION - DIGITAL AUDIO INTERFACE

The AV2722 can be operated in either master or slave mode. By default, the chip is set to operate in “Slave” mode.

To configure the chip for “Master” mode operation, the programming bit MASTER (CREG6[7]) must be pro-

grammed to “1”. In master mode operation, AV2722 acts as a master which generates SC, SFAD, and SFDA. In

slave mode operation, AV2722 receives these signals from an audio DSP encoder/decoder source.