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AV2722 Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers |
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AV2722 Datasheet(HTML) 13 Page - List of Unclassifed Manufacturers |
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13 / 29 page ![]() AV2722 (Preliminary) 13-29 January 22, 2004 REGULAR OR USB AUDIO DATA The AV2722 can be operated in regular (non-USB) or USB (Universal Serial Bus) modes. The usage of regular or USB applications are programmed via the 3-wire or 2-wire serial command port. The selection of sampling rates for regular or USB modes are controlled by CREG3[7:0]. Please refer to the section “Programmable Control Register Assignment” below. In regular audio application, the user selects an appropriate XCK clock which is generated by an off chip oscilla- tor.The user then program the chip for desired ADC, DAC sampling frequencies. By default, the chip is set to oper- ated at 48KHz sampling rate, 256fs for both the ADC and DAC, with XCK running at 12.288 MHz. The AV2722 supports sampling rates from 8KHz to 96 KHz for both ADC and DAC. For 192 KHz sampling rate, only the DAC path is operational. The ADC path is “turned off”. In USB system, the common USB clock frequency is 12 MHz. To use the AV2722 for USB application, XCK should be running at 12 MHz. PROGRAMMABLE CONTROL REGISTER ASSIGNMENT The are 13 Programmable Registers in the AV2722. The function and address assignment of these registers are described in the following table. All these programmable registers can be read back via the Serial Command Port. Address (7-bit hex) Register Default Value (hex) Register Function 0 VOLREG[7:0] 7F Volume value for both left and right channel 1 CREG1[7:0] 00 De-emphasis control 2 CREG2[7:0] 00 DAC path serial input port control 3 CREG3[7:0] 00 DAC, ADC sampling frequency selection control 4 CREG4[7:0] 00 DAC and miscellaneous power down control 5 CREG5[7:0] 40 DAC headphone control 6 CREG6[7:0] 00 ADC path serial output port control 7 CREG7[7:0] 03 ADC high-pass filter control 8 CREG8[7:0] 12 ADC path left channel gain and mute control 9 CREG9[7:0] 12 ADC path right channel gain and mute control A CREG10[7:0] 06 ADC power down control B CREG11[7:0] 00 ADC path left and right microphone gain control C CREG12[7:0] 00 Chip software reset |
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