¡ Semiconductor

ML2500

3/7

FEDL2500-01

PIN DESCRIPTIONS

Symbol

Type

Description

DI

I

Serial input pin for command data.

CS

I

Chip select pin. "L" level input enables data input/output through the serial

interface.

RESET

I

RESET input pin, resetting the serial interface circuit only. "L" level input to

this pin initializes the serial interface. Must input "L" pulse after each power-on.

ROSC

I

Insert a 30 kW resistor (Precision within ±1%) between this pin and the DGND pin.

The same resistor should also be inserted if an external clock is used.

The resistor value determines the frequency of the clock for control in this device.

SG

O

Analog reference voltage (Signal Ground Voltage) output pin. It is

recommendable to insert a capacitor smaller than 3300 pF between this pin and

the AGND pin. Loads except for capacitors should not be connected to this pin.

LIN

I

Inverting input pin for the internal OP amplifier. Non-inverting input pin is

internally connected to SG voltage.

MON

O

Output "H" level during recording/playback operation.

TEST1

I

LSI's testing pin. Must be connected to DGND.

Pin

5

3

2

15

26

31

7

24

DO

O

Serial output pin for status data.

6

SCK

I

Shift clock input pin for the DI and the DO pins.

4

EXTCLK

I

External clock input pin. Allowable clock frequency range is 4.0 MHz to 8.192

MHz. When external clock is unused and internal oscillation clock in used,

connect this pin to the DGND.

8

LOUT

O

Output pin from the internal OP amplifier.

30

AOUT

O

Analog waveform output. Connect to an amplifier to drive a SP.

27

TEST2

O

Pins for testing the LSI. Must be held "OPEN".

11, 13, 18,

20, 22, 28, 29

—

Digital power supply pin. Insert a 0.1 mF or larger by-pass capacitor between

this pin and the DGND pin .

1

DGND

—

Digital Ground pin.

16

—

Analog power supply pin. Insert a 0.1 mF or larger by-pass capacitor between

this pin and the AGND pin.

32

AGND

—

Analog Ground pin.

17