SDA

SCL

Data Line Stable

Data Valid

Change of Data Allowed

16

DAC53608, DAC43608

SLASEQ4 – OCTOBER 2018

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Programming (continued)

2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

(R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 7. All

devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the

slave device with a matching address generates an acknowledge by pulling the SDA line low during the

with a slave has been established.

3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In

either case, the receiver must acknowledge the data sent by the transmitter. So the acknowledge signal can

be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data

sequences consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.

4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 6). This action releases the bus and stops the communication

stop condition, the bus is released, and all slave devices then wait for a start condition followed by a

matching address.