DAC53608 datasheet(13/32 Pages) TI1

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DAC53608, DAC43608

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SLASEQ4 – OCTOBER 2018

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Feature Description (continued)

8.3.1.3 CLR Functionality

The CLR pin is an asynchronous input pin to the DAC. When this pin is pulled low (logic 0), the DAC buffers and

the DAC latches to zero code.

8.3.1.4 Output Amplifier

The output buffer amplifier can generate rail-to-rail voltages on the output. The result is a maximum output range

of 0 V to VDD. The full-scale output range for each channel is determined by the reference voltage (VREFIN)

(Equation 1).

The buffer amplifier is capable of driving a load of TBD k

Ω in parallel with TBD nF to GND. The typical slew rate

is TBD V/µs with a typical ¼ to ¾ settling time of TBD µs.

8.3.2 Reference

The DACx3608 requires an external reference to operate. However, the reference pin VREFIN and the supply pin

VDD can be tied together. The reference input pin voltage can range from 1.8 V to VDD. The typical input

impedance of this pin is when all the channels are powered on is 12.5 kΩ. The DACx3608 also includes

LOW_VREF bit in the DEVICE_CONFIG register. For improved static performance when VREFIN < 2.5 V, this bit

must be set to 1.

8.3.3 Power-on-Reset (POR)

The DACx3608 family of devices includes a power-on reset function that controls the output voltage at power up.

After the VDD supply has been established a POR event is issued. The POR causes all registers to initialize to

their default values and communication with the device is valid only after a 2-ms power-on-reset delay. The

default value for all DACs in the DACx3608 devices is zero-code. At power-up all output channel buffer amplifiers

start in power down to 10K mode until a power up command is issue by writing 0 to the per channel power down

registers.

A power failure on VDD also results in a power-on-reset event. As long as VDD remains above their specified high

threshold a power failure event will not occur. In order to ensure a VDD collapse is registered as such by the

device, these supplies must be below their corresponding low threshold for at least 1 ms. When the supplies

drop below their high threshold but remain over the lower one (shown as the undefined region Figure 4), the

device may or may not reset under all specified temperature and power-supply conditions.

DAC53608 Datasheet(PDF) 13 Page - Texas Instruments