Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

DAC53608 Datasheet(PDF) 21 Page - Texas Instruments

Click here to check the latest version.
Part # DAC53608
Description  Octal, 10-Bit or 8-Bit, I2C Interface, Buffered Voltage Output DACs in Tiny 3 횞 3 QFN Package
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC53608 Datasheet(HTML) 21 Page - Texas Instruments

Back Button DAC53608 Datasheet HTML 17Page - Texas Instruments DAC53608 Datasheet HTML 18Page - Texas Instruments DAC53608 Datasheet HTML 19Page - Texas Instruments DAC53608 Datasheet HTML 20Page - Texas Instruments DAC53608 Datasheet HTML 21Page - Texas Instruments DAC53608 Datasheet HTML 22Page - Texas Instruments DAC53608 Datasheet HTML 23Page - Texas Instruments DAC53608 Datasheet HTML 24Page - Texas Instruments DAC53608 Datasheet HTML 25Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 32 page
background image
21
DAC53608, DAC43608
www.ti.com
SLASEQ4 – OCTOBER 2018
Product Folder Links: DAC53608 DAC43608
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Table 9. DACx3608 Register Names
OFFSET
ACRONYM
REGISTER NAME
SECTION
00h
NOP
No Operation
NOP Register (offset = 00h)
01h
DEVICE_CONFIG
Device Configuration Register
DEVICE_CONFIG Register (offset =
01h)
02h
STATUS/TRIGGER
Status and Trigger Register
STATUS/TRIGGER Register (offset =
02h)
03h
BRDCAST
Broadcast Data Register
BRDCAST Register (offset = 03h)
08h - 0Fh
DACA_DATA
DACn Data Register
DACn_DATA Register (offset = 08h -
0Fh)
8.6.1 NOP Register (offset = 00h)
Figure 9. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Don't Care
W
Table 10. NOP Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-0
Don't Care
W
0000h
Don't Care
8.6.2 DEVICE_CONFIG Register (offset = 01h)
Figure 10. DEVICE_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Don't Care
0
0
LOW_
VREF
PDN-
Alll
PDNH
PDNG
PDNF
PDNE
PDND
PDNC
PDNB
PDNA
W
R/W
R/W
Table 11. DEVICE_CONFIG Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
Don't Care
W
0h
Don't Care
11-10
RESERVED
W
00
Reserved
9
LOW_VREF
R/W
0
Set to '1' when VREFIN < 2.5 V else set to '0'
8
PDN-All
R/W
0
Global power down bit, When set to '1', all channels and all bias
blocks are powered down
7-0
PDNn
R/W
00h
DACn in power down mode (Output buffers power down 10K to
AGND) when this bit is set to '1'
8.6.3 STATUS/TRIGGER Register (offset = 02h)
Figure 11. STATUS/TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Don't Care
DEVICE_ID
Don't
Care
Don't
Care
SW_RST
W
R
W
W
W
Table 12. STATUS/TRIGGER Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
Don't Care
W
0h
Don't Care
11-6
DEVICE_ID
R
000000
Device Identification number
5-4
Don't Care
W
0h
Don't Care



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com