AD9139 datasheet(39/56 Pages) AD

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Data Sheet

AD9139

START-UP ROUTINE

To ensure reliable start up of the AD9139, certain sequences

must be followed.

Device Configuration and Start-Up Sequence 1

Set fDCI = 600 MHz, fDATA = 1200 MHz, and interpolation to 1×.

Enable the PLL, and set fREF = 300 MHz.

Enable the inverse sinc filter.

Use the DLL-based interface mode and set DLL phase

offset = 0.

Derived PLL Settings

The following PLL settings are derived from the device configuration:

•

fDAC = 1200 × 1 = 1200 MHz.

•

fVCO= fDAC = 1200 MHz (1 GHz < fVCO < 2 GHz).

•

VCO divider = fVCO/fDAC = 1.

•

Loop divider = fDAC/fREF = 4.

Start-Up Sequence 1

Power up the device (no specific power supply sequence is

required).

Apply stable DAC clock.

Apply stable DCI clock.

Feed stable input data.

Issue hardware reset (optional).

/* Device configuration register write

sequence */

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device Startup Configuration */

/* Configure PLL */

0x14 → 0xE7 /* Configure PLL loop BW and charge

pump current */

0x15 → 0xC1 /* Configure VCO divider and loop

divider */

0x12 → 0xC0 /*Enable the PLL */

0x12 → 0x80

Wait 10ms

Read 0x16[7] /* Expect 1b if the PLL is locked

/* Configure Data Interface */

0x5E → 0xFE /* Turn off LSB delay cell */

0x0A → 0xC0 /* Enable the DLL and duty cycle

correction. Set DLL phase offset to 0 */

Read 0x0E[7:4] /* Expect 1000b if the DLL is

locked */

/* Configure Interpolation filter */

0x28 → 0x80 /* 1× interpolation */

/* Reset FIFO */

0x25 → 0x01

Read 0x25[1] /* Expect 1b if the FIFO reset is

complete */

Read 0x24 /* The readback should be one of the

three values: 0x30, 0x40, or 0x50 */

/* Enable Inverse SINC filter */

0x27 → 0x80

/* Power up DAC outputs */

0x01 → 0x00

Device Configuration and Start-Up Sequence 2

Set fDCI = 200 MHz, fDATA = 400 MHz, fDAC = 800 MHz, and

interpolation to 2×.

Disable PLL.

Enable the inverse sinc filter.

Use the delay line-based interface mode with a delay

setting of 0.

Start-Up Sequence 2

Power up the device (no specific power supply sequence is

required).

Apply stable DAC clock.

Apply stable DCI clock.

Feed stable input data.

Issue a hardware reset (optional).

/* Device configuration register write

sequence */

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device Startup Configuration */

/* Configure Data Interface */

0x5E → 0x00 /* Configure the delay setting */

0x5F → 0x60

0x0D → 0x16 /* DC couple DCI */

0x0A → 0x00 /* Turn off DLL and duty cycle

correction */

/* Configure Interpolation filter */

0x28 → 0x00 /* 2× interpolation */

/* Reset FIFO */

Follow the serial port FIFO reset procedure in

the FIFO Operation section.

/* Enable Inverse SINC filter */

0x27 → 0x80

/* Power up DAC outputs */

0x01 → 0x00

Rev. A | Page 39 of 56

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