LTC2249CUH datasheet(8/20 Pages) LINER

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LTC2249

2249f

operation with the outputs enabled. Connecting SHDN to

GND and OE to VDD results in normal operation with the

outputs at high impedance. Connecting SHDN to VDD and

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to VDD and OE to VDD

results in sleep mode with the outputs at high impedance.

OE (Pin 11): Output Enable Pin. Refer to SHDN pin

function.

D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,

25, 26, 27): Digital Outputs. D13 is the MSB.

OGND (Pin 20): Output Driver Ground.

OVDD (Pin 21): Positive Supply for the Output Drivers.

Bypass to ground with 0.1µF ceramic chip capacitor.

OF (Pin 28): Over/Under Flow Output. High when an over

or under flow has occurred.

MODE (Pin 29): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

straight binary output format and turns the clock duty

cycle stabilizer off. 1/3 VDD selects straight binary output

format and turns the clock duty cycle stabilizer on. 2/3 VDD

selects 2’s complement output format and turns the clock

duty cycle stabilizer on. VDD selects 2’s complement

output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 30): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 31): 1.5V Output and Input Common Mode Bias.

Bypass to ground with 2.2µF ceramic chip capacitor.

GND (Exposed Pad) (Pin 33): ADC Power Ground. The

exposed pad on the bottom of the package needs to be

soldered to ground.

PI FU CTIO S

FUNCTIONAL BLOCK DIAGRA

SHIFT REGISTER

AND CORRECTION

DIFF

REF

AMP

REF

BUF

2.2µF

1µF1µF

0.1µF

INTERNAL CLOCK SIGNALS

REFH

REFL

CLOCK/DUTY

CYCLE

CONTROL

RANGE

SELECT

1.5V

REFERENCE

FIRST PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

REFH

REFL

CLK

MODE

OGND

OVDD

2249 F01

INPUT

S/H

SENSE

VCM

AIN

–

AIN

2.2µF

THIRD PIPELINED

ADC STAGE

OUTPUT

DRIVERS

CONTROL

LOGIC

SHDN

D13

•

Figure 1. Functional Block Diagram

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