AD5721 datasheet(22/31 Pages) AD

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AD5761/AD5721

Data Sheet

Rev. C | Page 22 of 31

SERIAL INTERFACE

The AD5761/AD5721 4-wire (SYNC, SCLK, SDI, and SDO)

digital interface is SPI compatible. The write sequence begins

after bringing the SYNC line low, maintaining this line low until

the complete data-word is loaded from the SDI pin. Data is

loaded in at the SCLK falling edge transition (see Figure 2).

When SYNC is brought high again, the serial data-word is

decoded according to the instructions in Table 10. The

AD5761/AD5721 contain an SDO pin to allow the user to

daisy-chain multiple devices together or to read back the

contents of the registers.

Standalone Operation

The serial interface works with both a continuous and noncontinu-

ous serial clock. A continuous SCLK source can be used only when

SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used, and SYNC must be taken high

after the final clock to latch the data. The first falling edge of

SYNC starts the write cycle. Exactly 24 falling clock edges must

be applied to SCLK before SYNC is brought high again. If SYNC is

brought high before the 24th falling SCLK edge, the data written is

invalid. If more than 24 falling SCLK edges are applied before

SYNC is brought high, the input data is also invalid.

The input shift register is updated on the rising edge of SYNC.

For another serial transfer to take place, SYNC must be brought

low again. After the end of the serial data transfer, data is

automatically transferred from the input shift register to the

addressed register. When the write cycle is complete, the output

can be updated by taking LDAC low while SYNC is high.

Readback Operation

The contents of the input, DAC, and control registers can be

read back via the SDO pin. Figure 4 shows how the registers are

decoded. After a register has been addressed for a read, the next

24 clock cycles clock the data out on the SDO pin. The clocks

must be applied while SYNC is low. When SYNC is returned high,

the SDO pin is placed in tristate. For a read of a single register,

the no operation (NOP) function clocks out the data. Alternatively,

if more than one register is to be read, the data of the first register

to be addressed clocks out at the same time that the second register

to be read is being addressed. The SDO pin must be enabled to

complete a readback operation. The SDO pin is enabled by default.

Daisy-Chain Operation

For systems that contain several devices, use the SDO pin to

daisy-chain several devices together. Daisy-chain mode is useful

in system diagnostics and in reducing the number of serial

interface lines. The first falling edge of SYNC starts the write

cycle. SCLK is continuously applied to the input shift register

when SYNC is low. If more than 24 clock pulses are applied, the

data ripples out of the shift register and appears on the SDO line.

This data is clocked out on the rising edge of SCLK and is valid

on the falling edge.

By connecting the SDO of the first device to the SDI input of

the next device in the chain, a multidevice interface is constructed.

Each device in the system requires 24 clock pulses. Therefore,

the total number of clock cycles must equal 24 × N, where N is

the total number of AD5761/AD5721 devices in the chain. When

the serial transfer to all devices is complete, SYNC is taken high,

which latches the input data in each device in the daisy chain

and prevents any further data from being clocked into the input

shift register.

*ADDITIONAL PINS OMITTED FOR CLARITY.

CONTROLLER

DATA IN

SDI

SCLK

DATA OUT

SERIAL CLOCK

CONTROL OUT

SDO

SCLK

SDO

SCLK

SDO

SDI

SYNC

AD5761/

AD5721*

AD5761/

AD5721*

AD5761/

AD5721*

Figure 65. Daisy-Chain Block Diagram

HARDWARE CONTROL PINS

Load DAC Function (LDAC)

After data transfers into the input register of the DAC, there are

two ways to update the DAC register and DAC output. Depend-

ing on the status of both SYNC and LDAC, one of two update

modes is selected: synchronous DAC update or asynchronous

DAC update.

Synchronous DAC Update

In synchronous DAC update mode, LDAC is held low while

data is being clocked into the input shift register. The DAC

output is updated on the rising edge of SYNC.

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