AD5761/AD5721

Data Sheet

Rev. C | Page 24 of 31

REGISTER DETAILS

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input,

SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0),

four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively.

Table 8. AD5761 16-Bit Input Shift Register Format

MSB

LSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB0

0

Register address

Register data

1

X means don’t care.

Table 9. AD5721 12-Bit Input Shift Register Format

MSB

LSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB4

DB3 to DB0

0

Register address

Register data

XXXX1

1

X means don’t care.

Table 10. Input Shift Register Commands

Register Address

DB19

DB18

DB17

DB16

Command

0

0

0

0

No operation

0

0

0

1

Write to input register (no update)

0

0

1

0

Update DAC register from input register

0

0

1

1

Write and update DAC register

0

1

0

0

Write to control register

0

1

0

1

No operation

0

1

1

0

No operation

0

1

1

1

Software data reset

1

0

0

0

Reserved

1

0

0

1

Disable daisy-chain functionality

1

0

1

0

Readback input register

1

0

1

1

Readback DAC register

1

1

0

0

Readback control register

1

1

0

1

No operation

1

1

1

0

No operation

1

1

1

1

Software full reset

CONTROL REGISTER

The control register controls the mode of operation of the AD5761/AD5721. The control register options are shown in Table 11 and Table 12.

On power-up, after a full reset, or after a hardware reset, the output of the DAC is clamped to ground through a 1 kΩ resistor and the

output buffer remains in power-down mode. A write to the control register is required to configure the device, remove the clamp to

ground, and power up the output buffer.

When the DAC output range is reconfigured during operation, a software full reset command (see Table 26) must be written to the device

before writing to the control register.

Table 11. Write to Control Register

MSB

LSB

DB[23:21]

DB20

DB[19:16]

DB[15:11]

DB[10:9]

DB8

DB7

DB6

DB5

DB[4:3]

DB[2:0]

0

Register address

Register data

0

0100

CV[1:0]

OVR

B2C

ETS

0

PV[1:0]

RA[2:0]

1

X means don’t care.