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AM5706 Datasheet(PDF) 96 Page - Texas Instruments

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Part # AM5706
Description  Sitara Processors
PDF  395 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5706 Datasheet(HTML) 96 Page - Texas Instruments

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AM5706, AM5708
SPRS961D – AUGUST 2016 – REVISED JULY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Terminal Configuration and Functions
Copyright © 2016–2018, Texas Instruments Incorporated
Table 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
pr2_pru1_gpo3
PRU1 General-Purpose Output
O
AA5, N5
pr2_pru1_gpo4
PRU1 General-Purpose Output
O
AC4, N6
pr2_pru1_gpo5
PRU1 General-Purpose Output
O
J25, T4
pr2_pru1_gpo6
PRU1 General-Purpose Output
O
J24, T5
pr2_pru1_gpo7
PRU1 General-Purpose Output
O
C16, P4
pr2_pru1_gpo8
PRU1 General-Purpose Output
O
D14, P3
pr2_pru1_gpo9
PRU1 General-Purpose Output
O
B14, R2
pr2_pru1_gpo10
PRU1 General-Purpose Output
O
A18, R1
pr2_pru1_gpo11
PRU1 General-Purpose Output
O
B17, N2
pr2_pru1_gpo12
PRU1 General-Purpose Output
O
B16, P2
pr2_pru1_gpo13
PRU1 General-Purpose Output
O
B18, N1
pr2_pru1_gpo14
PRU1 General-Purpose Output
O
A19, P1
pr2_pru1_gpo15
PRU1 General-Purpose Output
O
E17, N3
pr2_pru1_gpo16
PRU1 General-Purpose Output
O
E16, N4
NOTE
PRU-ICSS has an internal wrapper multiplexing that allows MII_RT, EnDAT, and Sigma
Delta functionality to be muxed with the PRU GPI/O signals. See PRU-ICSS I/O Interface in
device TRM. Additionally, the EGPIO module can also be configured to export additional
functions to EGPIO pins in place of simple GPIO. See Enhanced General-Purpose
Module/Serial Capture Unit in Device TRM.
4.3.24 Emulation and Debug Subsystem
NOTE
For more information, see the On-Chip Debug Support / Debug Ports section of the Device
TRM.
Table 4-25. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
IO
L21
tdi
JTAG test data
I
L23
tdo
JTAG test port data
O
J20
tclk
JTAG test clock
I
K21
trstn
JTAG test reset
I
L22
rtck
JTAG return clock
O
K25
emu0
Emulator pin 0
IO
C21
emu1
Emulator pin 1
IO
C22
emu2
Emulator pin 2
IO
E14
emu3
Emulator pin 3
IO
F14
emu4
Emulator pin 4
IO
F13
emu5
Emulator pin 5
O
D8
emu6
Emulator pin 6
O
B7
emu7
Emulator pin 7
O
C7
emu8
Emulator pin 8
O
E8
emu9
Emulator pin 9
O
B8
emu10
Emulator pin 10
O
C8



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