Data Sheet

AD5722/AD5732/AD5752

Rev. F | Page 25 of 31

DAC REGISTER

The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel in which the data

transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5752 (see Table 18), DB15 to DB2 for the

AD5732 (see Table 19), and DB15 to DB4 for the AD5722 (see Table 20).

Table 18. Programming the AD5752 DAC Register

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to DB0

0

0

0

0

0

DAC address

16-bit DAC data

Table 19. Programming the AD5732 DAC Register

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to DB2

DB1

DB0

0

0

0

0

0

DAC address

14-bit DAC data

X

X

Table 20. Programming the AD5722 DAC Register

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

DAC address

12-bit DAC data

X

X

X

X

OUTPUT RANGE SELECT REGISTER

The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, and the

range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22).

Table 21. Programming the Required Output Range

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to DB3

DB2

DB1

DB0

0

0

0

0

1

DAC address

Don’t care

R2

R1

R0

Table 22. Output Range Options

R2

R1

R0

Output Range (V)

0

0

0

+5

0

0

1

+10

0

1

0

+10.8

0

1

1

±5

1

0

0

±10

1

0

1

±10.8