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AD5722/AD5732/AD5752

Data Sheet

Rev. F | Page 28 of 31

APPLICATIONS INFORMATION

+5 V/±5 V OPERATION

When operating from a single +5 V supply or a dual ±5 V supply,

an output range of +5 V or ±5 V is not achievable because suffi-

cient headroom for the output amplifier is not available. In this

situation, a reduced reference voltage can be used. For example,

a 2 V reference voltage produces an output range of +4 V or ±4 V,

and the 1 V of headroom is more than enough for full operation.

A standard value voltage reference of 2.048 V can be used to

produce output ranges of +4.096 V and ±4.096 V.

ALTERNATIVE POWER-UP SEQUENCE SUPPORT

There may be cases where it is not possible to use the

recommended power-up sequence, and in those instances an

external circuit shown in Figure 43 is recommended to be used.

The circuit shown in Figure 43 ensures that the digital block is

powered up first, prior to the analog block, by using a load

switch circuit. This circuit targets applications for which either

AVDD or AVSS or both supplies power up before DVCC.

Consider the following design rules when choosing the

component values for the AVDD delay circuit.



R1 ensures that the Q1 gate to source voltage is zero when

DVCC is in an open state. R1 also prevents false turn on of

Q1. However, if DVCC is permanently connected to the

source, R1 can be removed to conserve power.



Select Q1 (N-channel MOSFET) with a VGS threshold that

is much lower than the minimum operating DVCC and a

VDS rating much lower than the maximum operating AVDD.



C1, R2, and R3 are the main components that dictates the

delay from DVCC enable to AVDD. Adjust the values

according for the desired delay. Choose R2 and R3 values

that ensure Q2 turn on.

































DELAY

)

(

)

sec

(

where



















Q2 (P-channel MOSFET) acts as a switch that allows the flow

of current from VIN to AVDD; therefore, choosing a MOSFET

with very low RDSON is necessary to minimize losses during

operation. Other parameters such as maximum VDS rating,

maximum drain to source current rating, VGS threshold

voltage, and maximum gate to source voltage rating must

also be taken into consideration when choosing Q2.

VIN

AVDD

DVCC

LOAD SWITCH

SECTION

CONTROL

SECTION

Figure 43. Load Switch Control Circuit

Figure 44 shows an example of the analog supplies powering up

before the digital supply. The circuit delays the AVDD power up

until after DVCC, as shown by the AVDD (delayed) line.

AVDD

AVSS

DVCC

AVDD (DELAYED)

t (sec)

Figure 44. Delayed Power Supplies Sequence Example

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5722/AD5732/AD5752 are mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5722/AD5732/AD5752

are in a system where multiple devices require an AGND-to-

DGND connection, the connection should be made at one

point only. The star ground point should be established as close

as possible to the device.

The AD5722/AD5732/AD5752 should have ample supply bypass-

ing of a 10 μF capacitor in parallel with a 0.1 μF capacitor on

each supply located as close to the package as possible, ideally

right up against the device. The 10 μF capacitor is the tantalum

bead type. The 0.1 μF capacitor should have low effective series

resistance (ESR) and low effective series inductance (ESI) such

as the common ceramic types, which provide a low impedance

path to ground at high frequencies to handle transient currents

due to internal logic switching.

The power supply lines of the AD5722/AD5732/AD5752 should

use as large a trace as possible to provide low impedance paths

and reduce the effects of glitches on the power supply line. Fast

switching signals, such as a data clock, should be shielded with

digital ground to avoid radiating noise to other parts of the

board, and they should never be run near the reference inputs.

A ground line routed between the SDIN and SCLK lines helps

reduce crosstalk between them (this is not required on a

multilayer board that has a separate ground plane, but separating

the lines does help). It is essential to minimize noise on the

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