FPD33584 datasheet(9/30 Pages) NSC

9 / 30 page

Functional Description (Continued)

When POL is low, odd numbered outputs (1, 3, 5,... 383)

are controlled by VGMA6 through VGMA10 and even num-

bered outputs are controlled by VGMA1 through VGMA5.

When POL is high, odd numbered outputs are controlled by

VGMA1 through VGMA5 and even numbered outputs are

controlled by VGMA6 through VGMA10. The POL signal for

line #n is sampled at the rising edge of CLK1 on line #n−1.

DIO1/DIO2 — Data Loading Enable 1 and 2 (I/O)

The DIO1 and DIO2 pins allow several FPD33584 column

drivers to be daisy chained together. The start pulse (SP or

STH) from the timing controller is connected to the input

DIOx pin on the first column driver in the chain. The input

DIO for the remaining column drivers in the chain are con-

nected to the output DIO from the preceding column driver.

The SHL pin controls whether DIO1 or DIO2 is configured as

the input.

If SHL is high, then the DIO1 pin is configured as an input

and the DIO2 pin as an output. If SHL is low, the DIO2 pin is

configured as an input and the DIO1 pin as an output.

The input DIOx pulse is latched on the falling edge of CLKP

DATPOL — Digital Data Invert (input)

When DATPOL is high, RSDS data is inverted. The DATPOL

pin can be tied either high or low through connection to a

neighboring pin on a custom package eliminating the need to

connect the pin to the PCB.

SHL — Data Shift Direction (input)

The SHL pin controls the data load direction. When SHL is

high, the data is loaded from output 1 to output 384, DIO1 is

configured as an input, and DIO2 is configured as an output.

When SHL is low, the data is loaded from output 384 to

output 1, DIO2 is configured as an input, and DIO1 is con-

figured as an output. The SHL pin can be tied off in the

custom package, eliminating the need to connect it to the

PCB.

RPI1/ RPI2 — Repair Amp Input 1 and 2 (input)

The input signal for the repair line buffers. These buffers are

optional and when not used, the input should be tied to

ground. RPI1 and RPI2 can be tied to ground with a connec-

tion in the package, eliminating the need to connect them to

the PCB.

RPO1/ RPO2 — Repair Amp Output 1 and 2 (output)

The output of the repair line buffers. These outputs are

current buffered copies of their respective inputs. When not

in use, RPO1 and RPO2 can be left unconnected.

TIME0/ TIME1 — Charge Share Time Select Pins (input)

The TIME0 and TIME1 pins define the length of charge

share time. Table 1 lists the charge share time options

defined by TIME0 and TIME1. Both of these pins have

internal pull-down resistors and default to a logic low state.

They can also be tied high in the package, eliminating the

need to connect them to the PCB.

GMA1–VGMA10 — RDAC References (input)

The reference voltages to the upper and lower RDACs used

to control the inverse gamma transfer function of the driver.

Option - Any or all of the inputs V

GMA2 through VGMA4 and

GMA7 through VGMA9 can be left undriven (floating).

DD1 — Digital Voltage Supply (power)

Positive supply voltage for the digital logic functions of the

driver. Nominally 3.3V.

DD2 — Analog Voltage Supply (power)

Positive supply voltage for the analog functions of the driver.

Nominally between 8.0 and 10.0V

SS1 — Digital Ground (power)

Digital ground reference voltage. Typically tied to V

SS2 on

the PCB.

SS2 — Analog Ground (power)

Analog ground reference voltage. Typically tied to V

SS1 on

the PCB

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