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Data Sheet

AD5301/AD5311/AD5321

Rev. C | Page 17 of 24

POWER-DOWN MODES

The AD5301/AD5311/AD5321 have very low power consump-

tion, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW

with a 5 V supply. Power consumption can be further reduced

when the DAC is not in use by putting it into one of three

power-down modes, which are selected by Bit 13 and Bit 12 (PD1

and PD0) of the control word. Table 6 shows how the state of

the bits corresponds to the mode of operation of the DAC.

Table 6. PD1 and PD0 Operating Modes

PD1

PD0

Operating Mode

Normal operation

Power-down (1 kΩ load to GND)

Power-down (100 kΩ load to GND)

Power-down (three-state output)

The software power-down modes programmed by PD1 and

PD0 may be overridden by the PD pin on the 8-lead version.

Taking this pin low puts the DAC into three-state power-down

mode. If PD is not used, tie it high.

When both bits are set to 0, the DAC works normally with its

normal power consumption of 150 μA at 5 V, while for the three

power-down modes, the supply current falls to 200 nA at 5 V

(50 nA at 3 V). Not only does the supply current drop, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the device is known

while the device is in power-down mode and provides a defined

input condition for whatever is connected to the output of the

DAC amplifier. There are three different options. The output is

connected internally to GND through a 1 kΩ resistor, a 100 kΩ

resistor, or it is left three-stated. Resistor tolerance = ±20%.

The output stage is illustrated in Figure 35.

STRING DAC

AMPLIFIER

VOUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 35. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

DAC register are unchanged when in power-down. The time to

exit power-down is typically 2.5 μs for VDD = 5 V and 6 μs when

VDD = 3 V (see Figure 21).

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