UP9507 datasheet(17/28 Pages) UPI

17 / 28 page

uP9507

uP9507-DS-C3000, June. 2015

www.upi-semi.com

Conceptual

Functional Description

CSN

ISUM

OCP

OUT

Total Output OCP and Operating Phase Number

The total output OCP level is usually designed for the

voltage regulator that is operated in full phase condition by

hardware setting. The actual operating phase number is

controlled by the SVID SetPS command. When the

operating phase number is decreased, the total output OCP

level is decreased as well. The total output OCP level is

changed per actual operating phase number. Table 7 shows

the total output OCP ratio per actual operating phase

number and the hardware configuration.

Table 7. Total Output OCP and Operating Phase Number

-2

-1

Output Current Reporting

Refer to Figure 8, the sensed current I

CSN is also separately

mirrored and fed to IMON pin (IMONA for VccGT) as I

IMON

for SVID output current reporting function. Connect a resistor

IMON from IMON pin to GND. The current IIMON flows through

the resistor R

IMON, creating voltage drop across it. As the

total load current increases, the voltage on IMON pin (V

IMON)

increases proportionally. An internal analog-to-digital

converter (ADC) converts V

IMON to a digital content for output

current reporting through SVID interface. As V

IMON voltage

increases, the SVID register 0x15h content increases. The

IMON voltage has typically 600mV offset, which means

IMON = 600mV and SVID register 0x15h = 00h. The ADC

input range is typically 1.5V, which means the SVID register

0x15h = FFh when V

IMON = 2100mV. Further increase of

IMON (>2.1V) is allowed, but the ADC results will remain

at FFh. Capacitor can be added to the IMON pin to adjust

the response time of current reporting. The IMON pin is for

digital output current reporting only, not for SVID IccMAX

alert function or OCP. The total output current level for SVID

CSN

IMON

FFh

OUT

SVID

Note that the resistance value of R

IMON must be between

10k

Ω to 60kΩ to ensure the controller in normal operation.

IMON/IMONA Capacitor Selection

The capacitor C

IMON connected from IMON to GND (CIMONA

for IMONA) is used to adjust the response time of IMON

voltage change to load current change. It is recommended

to add a capacitor to the IMON pin. However, too large

capacitance for C

IMON is improper, and will affect the accuracy

in digital output current reporting. Due to the embedded A/

D conversion circuit to the IMON pin, the RC time constant

(tau) should be adequate to ensure correct operation and

digital current reporting accuracy. Use 4 x tau = 160us as

the rule of thumb to determine C

IMON. After resistor RIMON is

determined, the C

IMON is then calculated by

IMON

160

−

≤

Then choose a capacitance value that is closest to but not

greater than the calculation for C

IMON.

Over Voltage Protection (OVP)

The controller monitors the voltage on FB pin (FBA for

VccGT) for over voltage protection. The controller monitors

the voltage on FB pin (FBA for VccGT) for under voltage

protection. After output voltage ramps up to Vboot, the

controller initiates OVP function. Once V

FB exceeds VEAP

+ OVP threshold for a specific delay time, OVP is triggered.

VR_RDY will be pulled low immediately, UGx will be held

low, LGx will be held high, and PWM outputs will be low to

let driver turns on low side MOSFET and turns off high side

MOSFET to protect CPU. Since the low side MOSFET is

turned on, the regulator output capacitor will be discharged

and output voltage decreases as well. When FB pin voltage

decreases to lower than typical 0.5V, LGx will be held low

(PWM outputs turns to high impedance state) to turn off

the low side MOSFET to avoid negative output voltage.

The other unaffected voltage regulator will also shut down.

The OVP is a latch-off type protection, and it can only be

reset by VCC or EN toggling. The OVP detection circuit

has a fixed delay time to prevent false trigger.

Under Voltage Protection (UVP)

The controller monitors the voltage on FB pin (FBA for

VccGT) for under voltage protection. After output voltage

ramps up to Vboot, the controller initiates UVP function.

Once V

FB is lower than VEAP - UVP threshold for a specific

delay time, OVP is triggered. VR_RDY will be pulled low

immediately, both UGx and LGx will be held low, and all

PWM outputs will in high-impedance state to let driver turns

off all MOSFETs to shutdown the regulator. The other

unaffected voltage regulator will also shut down. The UVP

is a latch-off type protection, and it can only be reset by

VCC or EN toggling. The UVP detection circuit has a fixed

delay time to prevent false trigger.

Per-Phase Over Current Protection

In addition to the total output current OCP, the controller

provides per-phase current OCP to protect the voltage

regulator. The controller uses DCR current sensing

technique to sense the inductor current in each phase for

per-phase over current protection and current balance as

shown in Figure 9. In this inductor current sensing topology,

the time constant can expressed as follows.

CSX

CSPX

UP9507 Datasheet(PDF) 17 Page - uPI Group Inc.

UP9507 Datasheet(HTML) 17 Page - uPI Group Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL