MSM514262-80JS datasheet(33/45 Pages) OKI

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MSM514262

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PIN FUNCTION

Address Input : A0 - A8

The 18 address bits decode an 8-bit location out of the 262,144 locations in the MSM514262

memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard

DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column

address bits are latched at the falling edge of CAS.

Row Address Strobe : RAS

RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is

“high”. As the standard DRAM’s RAS signal function, RAS is control input that latches the row

address bits and a random access cycle begins at the falling edge of RAS.

In addition to the conventional RAS signal function, the level of the input signals, CAS, DT/OE,

WB/WE, DSF and SE at the falling edge of RAS, determines the MSM514262 operation modes.

Column Address Strobe : CAS

As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the

column address input and the state of the special function input DSF to select, in conjunction

with the RAS control, either read/write operations or the special block write feature on the

RAM port when the DSF is held “low” at the falling edge of RAS.

CAS also acts as a RAM port output enable signal.

Data Transfer/Output Enable : DT/OE

DT/OE is also a control input signal having multiple functions. As the standard DRAM’s OE

signal function, DT/OE is used as an output enable control when DT/OE is “high” at the falling

edge of RAS.

In addition to the conventional OE signal function, a data transfer operation is started between

the RAM port and the SAM port when DT/OE is “low” at the falling edge of RAS.

Write-per-Bit/Write Enable : WB/WE

WB/WE is a control input signal having multiple functions. As the standard DRAM’s WE

signal function, it is used to write data into the memory on the RAM port when WB/WE is

“high” at the falling edge of RAS.

In addition to the conventional WE signal function, the WB/WE determines the write-per-bit

function when WB/WE is “low” at the falling edge of RAS, during RAM port operations. The

WB/WE also determines the direction of data transfer between the RAM and SAM.

When WB/WE is “high” at the falling edge of RAS, the data is transferred from RAM to SAM

(read transfer). When WB/WE is “low” at the falling edge of RAS, the data is transferred SAM

to RAM (write transfer).

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