AP65550

Document number: DS36336 Rev. 5 - 2

2 of 16

www.diodes.com

January 2018

© Diodes Incorporated

AP65550

Typical Applications Circuit

AP65550

L1

1.5

μH

R1

8.25k

Ω

R2

22.1k

Ω

C5

0.1µF

C2

44

μF

C1

20

μF

C4

8.2nF

ON

OFF

VIN

SS

EN

VREG5

SW

BST

FB

C3

1µF

PGND

INPUT

OUTPUT

1.05V

12V

Figure 1 Typical Application Circuit

Pin Descriptions

Pin

Name

Pin Number

Function

SO-8EP

U-DFN3030-10

EN

1

1

Enable input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on

the regulator, drive it low to turn off. Pull up with 100k

Ω resistor to VIN for automatic startup.

FB

2

2

Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive

voltage divider connected to it from the output voltage.

VREG5

3

3

Internal power supply output pin to connect an additional capacitor. Connect a

1μF (typical)

capacitor as close as possible to the VREG5 and PGND. This pin is not active when EN is

low.

SS

4

5

Soft-start control input pin. SS controls the soft start period. Connect a capacitor from SS to

GND to set the soft-start period.

GND

5

6

Ground pin is the main power ground for the switching circuit.

SW

6

7, 8

Power Switching Output. SW is the switching node that supplies power to the output.

Connect the output LC filter from SW to the output load. Note that a capacitor is required

from SW to BST to power the high-side switch.

BST

7

4

Bootstrap pin. A bootstrap capacitor is connected between the BST pin and SW pin. The

voltage across the bootstrap capacitor drives the internal high-

side NMOS switch. A 0.1μF

(typical) capacitor is required for proper operation.

VIN

8

9, 10

Supply input pin. A capacitor should be connected between the VIN pin and PGND pin to

keep the DC input voltage constant.

PGND

9

(Exposed

Pad)

11

(Exposed Pad)

Power ground. Exposed pad must be connected to a single point GND and as large of

PGND plane as possible for maximum thermal performance.