LTC2436-1IGN datasheet(22/28 Pages) LINER

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LTC2436-1

24361f

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

IN+ and IN– and with the difference between the input and

reference common mode voltages. While the input drive

circuit nonzero source impedance combined with the con-

verter average input current will not degrade the INL

performance, indirect distortion may result from the modu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large CIN capacitor

values, it is advisable to carefully match the source imped-

ance seen by the IN+ and IN– pins. When FO = LOW

(internal oscillator and 50Hz/60Hz notch), every 60

Ω mis-

match in source impedance transforms a full-scale com-

mon mode input signal into a differential mode input

signal of 1LSB. When FO is driven by an external oscillator

with a frequency fEOSC, every 1Ω mismatch in source

impedance transforms a full-scale common mode input

signal into a differential mode input signal of 1.11 • 10–7

• fEOSCLSB. Figure 18 shows the typical offset error due to

input common mode voltage for various values of source

resistance imbalance between the IN+ and IN– pins when

large CIN values are used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typically better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/

°C) are

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (

±10nA max), results

in a small offset shift. A 15k source resistance will create

a 0LSB typical and 1LSB maximum offset voltage.

Reference Current

In a similar fashion, the LTC2436-1 samples the differen-

tial reference pins REF+ and REF– transfering small amount

of charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gain and INL performance. The effect of this current can be

analyzed in the same two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 0.01µF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Figure 18. Offset Error vs Common Mode Voltage

(VINCM = IN+ = IN–) and Input Source Resistance

Imbalance (

∆RIN = RSOURCEIN+ – RSOURCEIN–) for

Large CIN Values (CIN ≥ 1µF)

APPLICATIO S I FOR ATIO

VINCM (V)

0.5

1.5

2.5

3.5

4.5

24361 F18

–4

–8

FO = GND

TA = 25°C

RSOURCEIN– = 500Ω

CIN = 10µF

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = IN– = VINCM

∆RIN = +400Ω

∆RIN = +200Ω

∆RIN = +100Ω

∆RIN = 0Ω

∆RIN = –100Ω

∆RIN = –200Ω

∆RIN = –400Ω

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