VT6212 / VT6212L PCI USB2.0 Controller

Revision 1.06, December 7, 2005

-5-

Pin Descriptions

Pin Descriptions

Table 2. VT6212 / VT6212L Pin Descriptions

PCI Interface

Signal Name

Pin #

I/O Power

Signal Description

AD[31:0]

(see pin

list)

IO VCC33 Address and Data. Addresses are passed during the first clock cycle. Data is

passed in subsequent cycles.

CBE[3 :0]#

3, 19,

28, 41

IO VCC33 Command / Byte Enables. The command for the current cycle is driven with

FRAME# assertion. Byte enables corresponding to supplied or requested data are

then driven on following clocks.

PAR

27

IO VCC33 Parity. A single parity bit is provided over AD[31:0] and CBE[3:0]# to check that

the data has been transferred accurately..

IDSEL

6

I

VCC33 Initialization Device Select. Used as a chip select during configuration read and

write cycles.

DEVSEL#

23

IO VCC33 Device Select. As an output, this signal is asserted to claim PCI transactions

through positive or subtractive decoding.

As an input, DEVSEL# indicates the

response to a VT6212-initiated transaction and is also sampled when decoding

whether to subtractively decode the cycle.

FRAME#

20

IO VCC33 Cycle Frame. Assertion indicates the address phase of a PCI transfer. Negation

indicates that one more data transfer is desired by the cycle initiator.

STOP#

24

IO VCC33 PCI Stop. Asserted by the target (the VT6212 / VT6212L chip) to request the

master (PCI device) to stop the current transaction.

IRDY#

21

IO VCC33 Initiator Ready. Asserted when the initiator is ready for data transfer.

TRDY#

22

IO VCC33 Target Ready. Asserted when the target is ready for data transfer.

PCIRST#

111

I

VCC33 PCI Reset. When detected low, an internal hardware reset is performed. PCIRST#

assertion or deassertion may be asynchronous to PCICLK, however, it is

recommended that deassertion be synchronous to guarantee a clean and bounce free

edge.

PCICLK

109

I

VCC33 PCI Clock. 33 MHz. Used to clock all PCI bus transactions.

INTA#

105

O

VCC33 PCI Interrupt A. Asynchronous signal used to request an interrupt.

INTB#

106

O

VCC33 PCI Interrupt B. Asynchronous signal used to request an interrupt.

INTC#

107

O

VCC33 PCI Interrupt C. Asynchronous signal used to request an interrupt.

REQ#

113

O

VCC33 PCI Bus Request. Asserted by the VT6212 / VT6212L to request bus use.

GNT#

112

I

VCC33 PCI Bus Grant. Asserted by the bus arbiter to grant permission to the VT6212 /

VT6212L for access to the PCI bus for bus master operations.

Serial EEPROM Interface

Signal Name

Pin #

I/O Power

Signal Description

EECS

56

O

VCC33 EEPROM Chip Select. Connect to EEPROM EECS pin.

EECK

55

O

VCC33 EEPROM Clock. Connect to EEPROM EECK pin.

EEDI

50

O

VCC33 EEPROM Data In. Connect to EEPROM EEDI pin.

EEDO

49

I

VCC33 EEPROM Data Output. Connect to EEPROM EEDO pin.

Chipset South Bridge Interface

Signal Name

Pin #

I/O

Power

Signal Description

SMI#

60

O

VCC33

System Management Interrupt.

PME#

67

O

VCCSUS

Power Management Event Interrupt.