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ASX340 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers

Part # ASX340
Description  1/4-Inch Color NTSC/PAL Digital Image SOC with Overlay Processor
PDF  78 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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PDF: 171981479/Source: 8304342517
Aptina reserves the right to change products or specifications without notice.
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
14
© 2010 Aptina Imaging Corporation All rights reserved.
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Aptina Confidential and Proprietary
Preliminary
Pin Assignments
Pin 1 is not populated with a ball. That allows the device to be identified by an additional
marking.
Table 5:
Pin Assignments
1
2
3
4
5
6
7
8
AEXTCLK
GPIO13
DAC_REF
VDD
DOUT0VDD
VDD_PLL
BXTAL
VDD_IO
DOUT_LSB1
VAA
GND
DOUT2DOUT1VDD_IO
CGPIO12
DOUT_LSB0
TCK
TRST_N
GND
DOUT4DOUT3VDD_IO
D
GND
RESET_BAR
TDI
SPI_SCLK
GND
DOUT6DOUT5VDD
EFRAME_SYNC
SADDR
VDD_IO
SPI_SDI
AGND
PIXCLK
VDD
VDD_IO
FSCLK
SDATA
TMS
AGND
DAC_POS
ATEST2
FRAME_VALID
DOUT7
GVDD
TDO
VDD
VREG_BASE
DAC_NEG
ATEST1
LINE_VALID
VDD_IO
H
GND
SPI_CS_N
SPI_SDO
Reserved
VDD_DAC
VAA
VAA_PIX
VDD_IO
Table 6:
Reset/Default State of Interfaces
Name
Reset State
Default State
Notes
EXTCLK
Clock running or stopped
Clock running
Input
XTAL
N/A
N/A
Input
RESET_BAR
Asserted
De-asserted
Input
SCLK
N/A
N/A
Input. Must always be driven to a valid logic
level.
SDATA
High impedance
High impedance
Input/Output. A valid logic level should be
established by pull-up resistor.
SADDR
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be permanently tied to VDD_IO or
GND.
SPI_SCLK
High impedance.
Driven, logic 0
Output. Output enable is R0x0032[13].
SPI_SDI
Internal pull-up enabled.
Internal pull-up enabled
Input. Internal pull-up is permanently enabled.
SPI_SDO
High impedance
Driven, logic 0
Output enable is R0x0032[13].
SPI_CS_N
High impedance
Driven, logic 1
Output enable is R0x0032[13].
FRAME_VALID
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered up, sampled, then powered down
again as part of the auto-configuration
mechanism. See Note 2.
LINE_VALID
PIXCLK
High impedance
Driven, logic 0
Output. This interface disabled by default.
See Note 1.
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0



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