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STC15F101 Datasheet(PDF) 76 Page - List of Unclassifed Manufacturers

Part # STC15F101
Description  Operating voltage range: 3.8 ~ 5.5V or 2.4V ~ 3.6V (STC15L204EA series)
PDF  252 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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STC15F101 Datasheet(HTML) 76 Page - List of Unclassifed Manufacturers

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JMP
@A+DPTR
Function:
Jump indirect
Description:
Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer,
and load the resulting sum to the program counter. This will be the address for subsequent
instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-
order eight bits propagates through the higher-order bits. Neither the Accumulator nor the
Data Pointer is altered. No flags are affected.
Example:
An even number from 0 to 6 is in the Accumulator. The following sequence of instructions
will branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
MOV
DPTR, #JMP_TBL
JMP
@A+DPTR
JMP-TBL:
AJMP
LABEL0
AJMP
LABEL1
AJMP
LABEL2
AJMP
LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.
Bytes:
1
Cycles:
2
Encoding:
0 1 1 1
0 0 1 1
Operation:
JMP
(PC) ← (A) + (DPTR)
← (A) + (DPTR)
(A) + (DPTR)
JNB bit, rel
Function:
Jump if Bit is not set
Description:
If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example:
The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B).
The instruction sequence,
JNB
P1.3, LABEL1
JNB
ACC.3, LABEL2
will cause program execution to continue at the instruction at label LABEL2
Bytes:
3
Cycles:
2
Encoding:
0 0 1 1
0 0 0 0
bit address
rel. address
Operation:
JNB
(PC) ← (PC)+ 3
← (PC)+ 3
(PC)+ 3
IF (bit) = 0
THEN
(PC) ← (PC) + rel
← (PC) + rel
(PC) + rel
76



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