LD5760GS datasheet(13/20 Pages) LEADTREND

13 / 20 page

LD5760

11/05/2015

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5760-DS-02 November 2015

However, the total pulse width of the turn-on spike is

related to the output power, circuit design and PCB

layout.

It is strongly recommended to add a small R-C

filter (as shown in Fig. 16) for larger power application to

avoid the CS pin from being damaged by the negative

turn-on spike.

VCC

GND

LD5760

Can be removed if the negative

spike is not over spec. (-0.3V).

OUT

150ns

blanking time

Fig. 15

VCC

GND

LD5760

R-C filter is required when the negative

spike exceeds -0.3V or the total spike width

is over 300nS LEB period.

OUT

Fig. 16

Output Stage and Maximum Duty-Cycle

A CMOS buffer with output stage of typical 300mA

driving capability is incorporated to drive a power

MOSFET directly.

And the maximum duty-cycle of

LD5760 is limited to 85% to avoid the transformer

saturation.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431

on the secondary side through the photo-coupler to the

COMP pin of LD5760. Similar to UC384X, its input stage

is with a diode voltage offset to feed the voltage divider

with 1/4 ratio, that is,

)

(

COMP

)

PWM

(

COMPARATOR







A pull-high resistor is embedded internally to optimize

the external circuit.

Internal Slope Compensation

A fundamental issue of current mode control is the

stability problem when its duty-cycle is operated for

more than 50%. To stabilize the control loop, the slope

compensation is required in the traditional UC384X

design by injecting the ramp signal from the RT/CT pin

through a coupling capacitor. LD5760 has internal slope

compensation circuit to simplify the external circuit

design.

Oscillator and Switching Frequency

The LD5760 fixes the switching frequency at 65KHz

internally to optimize its performance in EMI, thermal

treatment, component sizes and transformer design.

Dual-Oscillator Green-Mode Operation

There

are

many

different

topologies

has

been

implemented in different chips for the green-mode or

power

saving

requirements

such

“burst-mode

control

”, “skipping-cycle mode”, “variable off-time control

“…etc. The basic operation theory of all these

approaches intended to reduce the switching cycles

under light-load or no-load condition either by skipping

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