LD7830GS datasheet(11/18 Pages) LEADTREND

11 / 18 page

LD7830

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7830-DS-01a

August 2012

IPEAK

TON

TDIS

Primary

Current

AUX

Voltage

VDS

-nAUX/nP ∙ VIN

Delay Time

-nAUX/nS ∙VOUT

VOUT

Minimum

Voltage Turn-on

OUT

VCOMP

RAMP

ZCD

Voltage

0.1V

-nAUX/nS ∙VOUT RZ1/(RZ1+RZ2)

-0.3V-Clamp

Secondary

Current

Fig. 16

Programming Maximum ON-time

LD7830 features adjustable maximum ON-time to limit

power output in abnormal operation. The selection of

maximum ON-time is subject to ZCD resistance as shown

in Fig. 17. ZCD resistance can be obtained from below:

ZCD

NVcc

RZ1

RZ2

ZCD







Fig. 17

The following table is a suggestion for maximum ON-time

setting.

RZCD

Max. Ton

Suggestion

(Typ.)

32k<RZCD

s

36k

28k<RZCD<32k

12.8

s

30k

24k<RZCD<28k

10.7

s

26k

20k<RZCD<24k

9.1

s

22k

16k<RZCD<20k

8.0

s

18k

12k<RZCD<16k

7.1

s

14k

8k<RZCD<12k

6.4

s

10k

RZCD<8k

5.8

s

High/ Low Line OCP Compensation

LD7830 supports high/low line OCP compensation

through aux-winding to reflect the magnitude of input

voltage. When gate turns on, ZCD pin will source the

current IZCD to clamp the voltage to zero as shown in

Fig.18. According to this current information, OCP trigger

level VCS-OFF will be determined by RZ1 and input voltage.

In order to avoid ZCD pin over rating, IZCD must be set

less than 2mA. IZCD-max can be calculated as below:

VCC

MAX

ZCD









ZCD

NVcc

RZ1

RZ2

IZCD

Fig. 18

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