LD7830GS datasheet(12/18 Pages) LEADTREND

12 / 18 page

LD7830

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7830-DS-01a

August 2012

The relation (typical) of VCS-OFF and IZCD is shown in Table

IZCD (A)

VCS-OFF (V)

160

0.5

160~200

0.475

200~240

0.4625

240~290

0.45

290~350

0.425

350~390

0.4

390~450

0.375

>450

0.35

Table 1

Output Drive Stage

With typical 500mA/-800mA driving capability,

an output

stage of a CMOS buffer is incorporated to drive a power

MOSFET directly.

The output voltage is clamped at 13V

to protect the MOSFET gate even when the VCC voltage

is higher than 13V.

Current

Sensing

and

Leading-edge

Blanking

The LD7830 detects the primary MOSFET current from

the CS pin, which is for the pulse-by-pulse current limit.

The maximum voltage threshold of the current sensing

pin is set at 0.5V. From above, the MOSFET peak current

can be obtained from below.

)

MAX

(

PEAK



A leading-edge blanking (LEB) time is included in the

input of CS pin to prevent the false-trigger from the

current spike. In the low power application, if the total

pulse width of the turn-on spikes is less than and the

negative spike on the CS pin doesn

’t exceed -0.3V, it

could eliminated the R-C filter.

However, the total pulse width of the turn-on spike is

determined by the output power, circuit design and PCB

layout.

It is strongly recommended to adopt a smaller

R-C filter for higher power application to avoid the CS pin

being damaged by the negative turn-on spike.

Over

Load

Protection

(OLP)

Auto

Recovery

To protect the circuit from damage due to overload

condition or output short condition, a smart OLP function

is implemented in the LD7830 for it. The OLP function is

an auto-recovery type protection. Fig. 19 shows the

waveforms of the OLP operation.

Under such fault

condition, the feedback system will force the voltage loop

toward saturation and thus pull up the voltage of COMP

pin (VCOMP).

If the VCOMP trips the OLP threshold of

4.8V and stays for over OLP delay time, the protection will

be activated to turn off the gate output and to shut down

the switching of power circuit.

The OLP delay time is to

prevent the false-trigger during the power-on and turn-off

transient.

A divided-by-4 counter is implemented to reduce the

average

power

consumption

under

OLP

behavior.

Whenever OLP is activated, the output is latched off and

the divided-by-4 counter starts to count the number of

UVLO(off). The latch will be released if the 4nd UVLO(off)

point is counted, and then the output recovers switching

again.

By using such protection mechanism, the average input

power can be reduced to a very low level so that the

component temperature and stress can be controlled

within a safe operating area.

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