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ES8388 Datasheet(PDF) 11 Page - Suzhou Everest Semiconductor Co. Ltd. |
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ES8388 Datasheet(HTML) 11 Page - Suzhou Everest Semiconductor Co. Ltd. |
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11 / 36 page ![]() Everest Semiconductor ES8388 Revision 5.0 July 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com 11 Table 3 Write Data to Register in 2-wire Interface Mode Chip Address R/W Register Address Data to be written start 001000 AD0 0 ACK RAM ACK DATA ACK Stop Figure 2a 2-wire Write Timing Table 4 Read Data from Register in 2-wire Interface Mode Chip Address R/W Register Address Start 001000 AD0 0 ACK RAM ACK Chip Address R/W Data to be read Start 001000 AD0 1 ACK Data NACK Stop Figure 2b 2-wire Read Timing 6 CONFIGURATION REGISTER DEFINITION SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total of 53 user programmable 8-bit registers in this device. These registers control the operations of ADC and DAC. External master controller can access these registers by using the slave address specified in RAM (Register Address Map) register as shown in the Table 5. Table 5 Bit Content of Register Address Map B7 B6 B5 B4 B3 B2 B1 B0 Reg. 00 SCPReset LRCM DACMCLK SameFs SeqEn EnRef VMIDSEL Reg. 01 LPVcmMod LPVrefBuf PdnAna PdnIbiasgen VrefrLo PdnVrefbuf |
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