ES8388 datasheet(13/36 Pages) EVEREST

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Everest Semiconductor

ES8388

Revision 5.0

July 2018

Latest datasheet: www.everest-semi.com or info@everest-semi.com

Reg. 43

slrck

Lrck_sel

offset_dis,

mclk_dis

Adc_dll_pwd

Dac_dll_pwd

Reg. 44

offset

Reg. 45

VROI

Reg. 46

LOUT1VOL

Reg. 47

ROUT1VOL

Reg. 48

LOUT2VOL

Reg. 49

ROUT2VOL

Reg. 50

Reg. 51

hpLout1_ref1

hpLout1_ref2

Reg. 52 spkLout2_ref1

spkLout2_ref2

mixer_ref1

mixer_ref2

MREF1

MREF2

6.1

Chip Control and Power Management

6.1.1

Bit Name

Bit

Description

SCPReset

0 – normal (default)

1 – reset control port register to default

LRCM

0 – ALRCK disabled when both ADC disabled; DLRCK disabled when both DAC disabled (default)

1 – ALRCK and DLRCK disabled when all ADC and DAC disabled

DACMCLK

0 – when SameFs=1, ADCMCLK is the chip master clock source (default)

1 – when SameFs=1, DACMCLK is the chip master clock source

SameFs

0 – ADC Fs differs from DAC Fs (default)

1 – ADC Fs is the same as DAC Fs

SeqEn

0 – internal power up/down sequence disable (default)

1 – internal power up/down sequence enable

EnRef

0 – disable reference

1 – enable reference (default)

VMIDSEL

1:0

00 – Vmid disabled

01 – 50 k

Ω divider enabled

10 – 500 k

Ω divider enabled (default)

11 – 5 k

Ω divider enabled

6.1.2

Bit Name

Bit

Description

LPVcmMod

0 – normal (default)

1 – low power

LPVrefBuf

0 – normal

1 – low power (default)

PdnAna

0 – normal

1 – entire analog power down (default)

PdnIbiasgen

0 – normal

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