Everest Semiconductor

ES8388

Revision 5.0

July 2018

Latest datasheet: www.everest-semi.com or info@everest-semi.com

2

1

BLOCK DIAGRAM.....................................................................................4

2

28-PIN QFN AND PIN DESCRIPTIONS....................................................5

3

TYPICAL APPLICATION CIRCUIT ............................................................7

4

CLOCK MODES AND SAMPLING FREQUENCIES..................................7

5

MICRO-CONTROLLER CONFIGURATION INTERFACE .........................9

5.1

SPI ......................................................................................................9

5.2

2-wire ................................................................................................10

6

CONFIGURATION REGISTER DEFINITION .......................................... 11

6.1

Chip Control and Power Management ..............................................13

6.1.1

Register 0 – Chip Control 1, Default 0000 0110 ..........................13

6.1.2

Register 1 – Chip Control 2, Default 0101 1100 ..........................13

6.1.3

Register 2 – Chip Power Management, Default 1100 0011.........14

6.1.4

Register 3 – ADC Power Management, Default 1111 1100 .........14

6.1.5

Register 4 – DAC Power Management, Default 1100 0000 ........15

6.1.6

Register 5 – Chip Low Power 1, Default 0000 0000....................15

6.1.7

Register 6 – Chip Low Power 2, Default 0000 0000....................15

6.1.8

Register 7 – Analog Voltage Management, Default 0111 1100....15

6.1.9

Register 8 – Master Mode Control, Default 1000 0000 ...............16

6.2

ADC Control ......................................................................................16

6.2.1

Register 9 – ADC Control 1, Default 0000 0000..........................16

6.2.2

Register 10 – ADC Control 2, Default 0000 0000........................17

6.2.3

Register 11 – ADC Control 3, Default 0000 0010 ........................17

6.2.4

Register 12 – ADC Control 4, Default 0000 0000........................18

6.2.5

Register 13 – ADC Control 5, Default 0000 0110 ........................18

6.2.6

Register 14 – ADC Control 6, Default 0011 0000 ........................19

6.2.7

Register 15 – ADC Control 7, Default 0010 0000........................19

6.2.8

Register 16 – ADC Control 8, Default 1100 0000 ........................19

6.2.9

Register 17 – ADC Control 9, Default 1100 0000 ........................20

6.2.10 Register 18 – ADC Control 10, Default 0011 1000 ......................20

6.2.11 Register 19 – ADC Control 11, Default 1011 0000 ......................20

6.2.12 Register 20 – ADC Control 12, Default 0011 0010 ......................21

6.2.13 Register 21 – ADC Control 13, Default 0000 0110 ......................22

6.2.14 Register 22 – ADC Control 14, Default 0000 0000......................22

6.3

DAC Control ......................................................................................22

6.3.1

Register 23 – DAC Control 1, Default 0000 0000........................22

6.3.2

Register 24 – DAC Control 2, Default 0000 0110........................23

6.3.3

Register 25 – DAC Control 3, Default 0010 0010........................23

6.3.4

Register 26 – DAC Control 4, Default 1100 0000........................24

6.3.5

Register 27 – DAC Control 5, Default 1100 0000........................24

6.3.6

Register 28 – DAC Control 6, Default 0000 1000........................24

6.3.7

Register 29 – DAC Control 7, Default 0000 0000........................24

6.3.8

Register 30 – DAC Control 8, Default 0001 1111 ........................25

6.3.9

Register 31 – DAC Control 9, Default 1111 0111 .........................25