MS51 datasheet(21/53 Pages) NUVOTON

21 / 53 page

MS51

Jan. 29, 2019

Page 21 of 53

Rev 1.00

6.3 System Reset

The system reset can be issued by one of the events listed below. These reset event flags can be

read from several register to determine the reset source. Hardware reset sourcces are from peripheral

signals. Software reset can trigger reset through setting control registers.



Hardware Reset Sources

–

Power-on Reset (POR)

–

Low level on the nRESET pin

–

Watchdog Time-out Reset (WDT Reset)

–

Low Voltage Reset (LVR)

–

Brown-out Detector Reset (BOD Reset)



Software Reset Sources

–

CHIP Reset will reset whole chip by writing 1 to SWRST (CHPCON [7])

6.3.1

Hardware Reset Sources

Power-On Reset and Low Voltage Reset

6.3.1.1

The MS51 incorporates an internal power-on reset (POR) and a low voltage reset (LVR). During a

power-on process of rising power supply voltage VDD, the POR or LVR will hold the MCU in reset

mode when VDD is lower than the voltage reference thresholds. This design makes CPU not access

program flash while the VDD is not adequate performing the flash reading. If an undetermined

operating code is read from the program flash and executed, this will put CPU and even the whole

system in to an erroneous state. After a while, VDD rises above the threshold where the system can

work, the selected oscillator will start and then program code will execute from 0000H. At the same

time, a power-on flag POF (PCON.4) will be set 1 to indicate a cold reset, a power-on process

complete. Note that the contents of internal RAM will be undetermined after a power-on. It is

recommended that user gives initial values for the RAM block.

The POF is recommended to be cleared to 0 via software to check if a cold reset or warm reset

performed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1

again. If the reset is a warm reset caused by other reset sources, POF will remain 0. User may take a

different course to check other reset flags and deal with the warm reset event. For detailed electrical

characteristics, refer to the table 35-7 and 35-8.

PCON

– Power Control

SMOD

SMOD0

LPR

POF

GF1

GF0

IDL

R/W

Address: 87H, All pagessPOR reset value: 0001 000b, other reset value: 000U 0000b

Bit

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