Rev. A

www.3peakic.com

1.6MHz Bandwidth, Low Noise Precision Op‐amps 

Pin Functions

-IN: Inverting Input of the Amplifier.

+IN: Non-Inverting Input of Amplifier.

OUT: Amplifier Output. The voltage range extends to

within mV of each supply rail.

is from 2.2V to 5.5V. Split supplies are possible as long

as the voltage between V+ and V– is between 2.2V and

5.5V. A bypass capacitor of 0.1μF as close to the part as

possible should be used between power supply pins or

between supply pins and ground.

ground. It can also be tied to a voltage other than

2.2V to 5.5V. If it is not connected to ground, bypass it

with a capacitor of 0.1μF as close to the part as

possible.

Operation

The TP2331/TP2332/TP2334 can operate from a single +2.2V to +5.5V power supply, or from ±1.1V to ±2.75V power

supplies. The power supply pin(s) must be bypassed to ground with a 0.1μF capacitor as close to the pin as possible.

This series are high-precision op amps with a CMOS input stage and an excellent set of DC and AC features. The

combination of tight maximum voltage offset, low offset tempco and very low input current make them ideal for use in

high-precision DC circuits. They feature low-voltage operation, low-power consumption, high-current drive with

rail-to-rail output swing and high-gain bandwidth product.

Applications Information

High Accuracy

The TP2331/TP2332/TP2334 maximum input offset voltage is 50μV (2μV, typ) at +25°C. The maximum temperature

coefficient of the offset voltage are guaranteed to be 2μV/°C. The parts have an input bias current of 0.3pA. Noise

characteristics are 13nV/√Hz, and a low frequency noise (0.1Hz to 10Hz) of 4.1μVp-p. The CMRR is 140dB, and the PSRR is

120dB. The combination is what is necessary for the design of circuits to process signals while keeping high signal-to-noise

ratios, as in stages preceding high-resolution converters, or when they are produced by sensors or transducers generating

very small outputs.

Rail-to-Rail Inputs and Outputs

The TP233x op amps are designed to be immune to phase reversal when the input pins exceed the supply voltages,

therefore providing further in-system stability and predictability. Figure 1 shows the input voltage exceeding the supply

voltage without any phase reversal.

Figure 1. No Phase Reversal