LM5026 datasheet(12/23 Pages) NSC

12 / 23 page

PWM Outputs (Continued)

The rising edge overlap or deadtime and the falling edge

overlap or deadtime are identical and are independent of

operating frequency or duty cycle. The magnitude of the

overlap/deadtime can be calculated as follows:

Overlap Time = 2.8 x R

SET +2

Deadtime = 2.9 x R

SET +14

With R

SET in K Ohms and overlap / deadtime in nanosec-

onds

Gate Driver Outputs

The LM5026 provides two gate driver outputs, the main

power switch control (OUT_A) and the active clamp switch

control (OUT_B). The main gate driver features a compound

configuration, consisting of both MOS and bipolar devices,

which provide superior gate drive characteristics. The bipolar

device provides most of the drive current capability and sinks

a relatively constant current, which is ideal for driving large

power MOSFETs. As the switching event nears conclusion

and the bipolar device saturates, the internal MOS device

provides a low impedance to compete the switching event.

During turn-off at the Miller plateau region, typically between

2V - 4V, the voltage differential between the output and

PGND is small and the current source characteristic of the

bipolar device is beneficial to reduce the transition time.

During turn-on, the resistive characteristics of a purely MOS

gate driver is adequate since the supply to output voltage

differential is fairly large in the Miller region.

PWM Comparator/Slope

Compensation

The PWM comparator modulates the pulse width of the

controller output by comparing the current sense ramp signal

to the loop error signal. This comparator is optimized for

speed in order to achieve minimum controllable duty cycles.

The loop error signal is input into the controller in the form of

a control current into the COMP pin. The COMP pin control

current is internally mirrored by a matched pair of NPN

transistors which sink current througha5k

Ω resistor con-

nected to the 5V reference. The resulting error signal passes

through a 1.4V level shift and a gain reducing 3:1 resistor

divider before being applied to the pulse width modulator.

The opto-coupler detector can be connected between the

REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across

the optocoupler detector is nearly constant. The bandwidth

limiting phase delay which is normally introduced by the

significant capacitance of the opto-coupler is greatly re-

duced. Greater system loop bandwidth can be realized,

since the bandwidth-limiting pole associated with the opto-

coupler is now at a much higher frequency. The PWM com-

parator polarity is configured such that with no current into

the COMP pin, the controller produces the maximum duty

cycle at the main gate driver output.

20147913

FIGURE 2. PWM Output Phasing / Timing

20147914

FIGURE 3. Compound Gate Driver

LM5026 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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