LM5026 datasheet(14/23 Pages) NSC

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Maximum Duty Cycle Clamp

(Continued)

Soft-Start/Soft-Stop

The soft-start circuit allows the regulator to gradually reach a

steady state operating point, thereby reducing start-up

stresses and current surges. Upon turn-on, the SS pin ca-

pacitor is discharged by an internal switch. When the UVLO,

VCC and REF pins reach their operating thresholds, the SS

capacitor is released and charged with a 50uA current

source. The PWM comparator control voltage is clamped to

the SS pin voltage. When the PWM input reaches 1.4V,

output pulses commence with slowly increasing duty cycle.

The voltage at the SS pin eventually increases to 5V, while

the voltage at the PWM comparator increases to the value

required for regulation determined by the voltage feedback

loop.

If the UVLO pin voltage falls below the 1.25V standby thresh-

old but above the 0.4V shutdown threshold, the 50uA SS pin

source current is disabled and a 50uA sink current dis-

charges the soft-start capacitor. As the SS voltage falls and

clamps the PWM comparator input, the PWM duty cycle will

gradually fall to zero. This soft-stop feature produces a

gradual reduction of the power converter output voltage. This

gradual discharge of the output filter prevents oscillations in

the self-driven synchronous rectifiers on the secondary side

of the converter during turn-off.

Current Sense/Current Limit

The CS input provides a control ramp for the pulse width

modulator and current limit detection for overload protection.

If the sensed voltage at the CS comparator exceeds 0.5V the

present cycle is terminated (cycle-by-cycle current limit

mode).

A small RC filter, located near the controller, is recom-

mended for the CS input pin. An internal FET connected to

the CS input discharges the current sense filter capacitor at

the conclusion of every cycle to improve dynamic perfor-

mance. This same FET remains on for an additional 100nS

at the start of each main switch cycle to attenuate the leading

edge spike in the current sense signal.

The CS comparator is very fast and may respond to short

duration noise pulses. Layout considerations are critical for

the current sense filter and sense resistor. The capacitor

associated with the CS filter must be placed very close to the

device and connected directly to the pins of the LM5026 (CS

and AGND pins). If a current sense transformer is used, both

leads of the transformer secondary should be routed to the

filter network, which should be located close to the IC. If a

sense resistor located in the source of the main switch

MOSFET is used for current sensing, a low inductance type

of resistor is required. When designing with a current sense

resistor, all of the noise sensitive low power ground connec-

tions should be connected together near the AGND pin and

a single connection should be made to the power ground

(sense resistor ground point).

Overload Protection Timer

The LM5026 provides a current limit restart timer to disable

the outputs and force a delayed restart (hiccup mode) if a

current limit condition is repeatedly sensed. The number of

cycle-by-cycle current limit events required to trigger the

restart is programmable by means of an external capacitor at

the RES pin. During each PWM cycle the LM5026 either

sources or sinks current from the RES pin capacitor. If no

current limit is detected during a cycle, a 10uA discharge

current sink is enabled to hold the RES pin at ground. If a

current limit is detected, the 10uA sink current is disabled

and a 10 uA current source causes the voltage at RES pin to

gradually increase. In the event of an extended overload

condition, the LM5026 protects the converter with cycle-by-

cycle current limiting while the voltage at RES pin increases.

If the RES voltage reaches the 2.5V threshold, the following

restart sequence occurs (see Figure 7):

•

The RES capacitor and SS capacitors are fully dis-

charged.

•

The soft-start current source is reduced from 50 µA to 1

µA

•

The SS capacitor voltage slowly increases. When the SS

voltage reaches 1.4V, the PWM comparator will produce

the first output pulse. After the first pulse occurs, the SS

source current reverts to the normal 50 µA level. The SS

voltage increases at its normal rate gradually increasing

the duty cycle of the output drivers

•

If the overload condition persists after restart, cycle-by-

cycle current limiting will cause the voltage on the RES

capacitor to increase again, repeating the hiccup mode

sequence.

•

If the overload condition no longer exists after restart, the

RES pin will be held at ground by the 10 µA current sink

and normal operation resumes.

The overload timer function is very versatile and can be

configured for the following modes of protection:

Cycle-by-cycle only: The hiccup mode can be com-

pletely disabled by connecting the RES pin to AGND. In

this configuration, the cycle-by-cycle protection will limit

the output current indefinitely and no hiccup sequences

will occur.

Hiccup only: The timer can be configured for immediate

activation of a hiccup sequence upon detection of an

overload by leaving the RES pin open circuit.

20147917

FIGURE 6. Maximum Duty Cycle vs UVLO Voltage

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