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MSM7583

¡ Semiconductor

PIN AND FUNCTIONAL DESCRIPTIONS

TXD

Transmit data input for 384 kbps.

TXCI

Transmit clock input.

When the control register CR0 - B6 is “0”, a 384 kHz clock pulse synchronous with TXD should

be input to this pin. This clock pulse should be continuous because this device uses APLL to

generate internal clock pulses.

When CR0 - B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz

clock pulse is applied to TXCI, TXCO outputs a 384 kHz clock pulse, which is generated by

dividing the TXCI input by 10. The transmit data, synchronous 384 kHz clock pulse, should be

input to the TXD. In this case the device does not use APLL, and the 3.84 MHz clock pulse need

not be continuous. (Refer to Fig. 1.)

TXCO

Transmit clock output.

When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring

purposes. When CR0 - B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing

the TXCI input by 10. (Refer to Fig. 1.)

TXW

Transmit data window signal input.

The transmit timing signal for the burst data is input to the device through this pin. If TXW pin

is “1”, modulation data is output. (Refer to Fig. 1.)

I+, I–

Quadrature modulation signal I component differential analog outputs.

The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load

conditions are: R

≥ 10 kW, C £ 20 pF. The gain of these pins can be adjusted using the control

registers CR1 - B7 to B4, and the offset voltage at the I– pin can be adjusted using CR3 - B7 to

B3.

Q+, Q–

Quadrature modulation signal Q component differential analog outputs.

The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load

conditions are: R

≥ 10 kW , C £ 20 pF. The gain of these pins can be adjusted using the control

registers CR1 - B3 to B0, and the offset voltage at the Q– pin can be adjusted using CR4 - B7 to

B3.