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MSM9405

¡ Semiconductor

• DSR: DMA Mode Select Register (Address = 7h)

The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When

the system is reset, all bits of DSR are set to "0".

DSR

7

DSR

6

DSR

5

DSR

4

DSR

3

DSR

2

DSR

1

DSR

0

DMA_EN ("1": DMA mode)

Not Used

DSR Bit

DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value

is set to "0".

MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert

condition is met.)

performed. (DREQ is not asserted even if the DREQ assert condition is met.)

DSR[0]

Description

DSR[1-2]

DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC.

Function

0

0

DREQ becomes active low and DACK becomes active high.

When the RD signal becomes active while DACK is active,

the DMA read cycle (MemoryÆM9405) is selected. When

the WR signal becomes active while DACK is active, the

DMA write cycle (M9405ÆMemory) is selected. While

DACK is being asserted, address "0" (TDR/RDR) is

0

1

DREQ becomes active high and DACK becomes active low.

When the WR signal becomes active while DACK is active,

the DMA read cycle (MemoryÆM9405) is selected. When

the RD signal becomes active while DACK is active, the

DMA write cycle (M9405ÆMemory) is selected. While

DACK is being asserted, address "0" (TDR/RDR) is

1

0

DREQ becomes active low and DACK becomes active high.

DACK is disabled.

1

1

DREQ becomes active high and DACK becomes active low.

DACK is disabled.

These bits are not used.

DSR[3-7]