GPCL A1/B1 Series

© Generalplus Technology Inc.

Proprietary & Confidential

16

Sep. 15, 2015

Version: 1.0

10. LAYOUT GUIDELINE

PCB layout guidelines:

1.

The chip should be placed to where it makes VSSIN as close as possible to PCB pin out.

2.

Make the width of VSSIN, VDDO and Lpump's PCB pin out as wide as possible.

3.

The substrate under chip requires holes to dissipate heat and please connect substrate with VSS.

4.

The route through chip, battery, and inductor should be as short as possible; its wire diameter should be as thick as possible.

5.

Connect the VSS and battery's negative to a whole GND.

6.

Place all chip's components as close as possible to IC, especially the 47uF capacitor to VDDO. ESR<2 ohm in 0~70C is suggested.

7.

Please use inductance with lower resistance to gain higher efficiency. 22uH/0.5W@IDC(max)>250mA ,DCR<1.5ohm is the suggested

inductance specification.