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82801E Datasheet(PDF) 54 Page - Intel Corporation

Part # 82801E
Description  Intel 82801E Communications I/O Controller Hub (C-ICH)
PDF  84 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82801E Datasheet(HTML) 54 Page - Intel Corporation

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Intel® 82801E C-ICH
54
Advance Information Datasheet
EE0_DOUT,
EE1_DOUT
LAN I/O
RSM_PWROK
High
Running
EE0_SHCLK,
EE1_SHCLK
LAN I/O
RSM_PWROK
Low
Running
LAN0_RSTSYNC,
LAN1_RSTSYNC
LAN I/O
RSM_PWROK
High
Defined
LAN0_TXD[2:0],
LAN1_TXD[2:0]
LAN I/O
RSM_PWROK
Low
Defined
IDE Interface
PDA[2:0], SDA[2:0]
Main I/O
PCIRST#
Low
Undefined
PDCS1#, PDCS3#
Main I/O
PCIRST#
High
High
PDD[15:0], SDD[15:0]
Main I/O
PCIRST#
High-Z
High-Z
PDDACK#, SDDACK#
Main I/O
PCIRST#
High
High
PDIOR#, PDIOW#
Main I/O
PCIRST#
High
High
SDCS1#, SDCS3#
Main I/O
PCIRST#
High
High
SDIOR#, SDIOW#
Main I/O
PCIRST#
High
High
Interrupts
PIRQ[A:H]#
Main I/O
PCIRST#
High-Z
High-Z
SERIRQ
Main I/O
PCIRST#
High-Z
High-Z
APICD[1:0]
Main I/O
PCIRST#
High-Z
High-Z
USB Interface
USBP0P, USBP0N,
USBP1P, USBP1N
Main I/O
RSMRST#
High-Z
High-Z
Processor Interface
A20M#
CPU I/O
PCIRST#
See Note 1
High
CPUPWRGD
Main I/O
PCIRST#
See Note 3
High-Z
CPUSLP#
CPU I/O
PCIRST#
High
High
IGNNE#
CPU I/O
PCIRST#
See Note 1
High
INIT#
CPU I/O
PCIRST#
High
High
INTR
CPU I/O
PCIRST#
See Note 1
Low
NMI
CPU I/O
PCIRST#
See Note 1
Low
SMI#
CPU I/O
PCIRST#
High
High
Table 32. Power Plane and States for Output and I/O Signals (Sheet 2 of 3)
Signal Name
Power Plane
Reset Signal
During Reset
Immediately
after Reset
NOTES:
1. The 82801E C-ICH sets these signals at reset for processor frequency strap.
2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK
signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low
to High-Z.
4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this
point, they will be driven to their default (High) state.



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