Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

GS3471 Datasheet(PDF) 142 Page - Semtech Corporation

Part # GS3471
Description  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 Datasheet(HTML) 142 Page - Semtech Corporation

Back Button GS3471 Datasheet HTML 138Page - Semtech Corporation GS3471 Datasheet HTML 139Page - Semtech Corporation GS3471 Datasheet HTML 140Page - Semtech Corporation GS3471 Datasheet HTML 141Page - Semtech Corporation GS3471 Datasheet HTML 142Page - Semtech Corporation GS3471 Datasheet HTML 143Page - Semtech Corporation GS3471 Datasheet HTML 144Page - Semtech Corporation GS3471 Datasheet HTML 145Page - Semtech Corporation GS3471 Datasheet HTML 146Page - Semtech Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 142 / 179 page
background image
GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
142 of 179
Semtech
www.semtech.com
A09
INT_ENABLE
RSVD
15:8
—
—
Reserved.
EN_ADPG8_DET
7:7
RW
0
Interrupt mask enable for ADPG8_DET
pulse.
When enabled, interrupt will assert when
ADPG8_DET is set.
EN_ADPG7_DET
6:6
RW
0
Interrupt mask enable for ADPG7_DET
pulse.
When enabled, interrupt will assert when
ADPG7_DET is set.
EN_ADPG6_DET
5:5
RW
0
Interrupt mask enable for ADPG6_DET
pulse.
When enabled, interrupt will assert when
ADPG6_DET is set.
EN_ADPG5_DET
4:4
RW
0
Interrupt mask enable for ADPG5_DET
pulse.
When enabled, interrupt will assert when
ADPG5_DET is set.
EN_ADPG4_DET
3:3
RW
0
Interrupt mask enable for ADPG4_DET
pulse.
When enabled, interrupt will assert when
ADPG4_DET is set.
EN_ADPG3_DET
2:2
RW
0
Interrupt mask enable for ADPG3_DET
pulse.
When enabled, interrupt will assert when
ADPG3_DET is set.
EN_ADPG2_DET
1:1
RW
0
Interrupt mask enable for ADPG2_DET
pulse.
When enabled, interrupt will assert when
ADPG2_DET is set.
EN_ADPG1_DET
0:0
RW
0
Interrupt mask enable for ADPG1_DET
pulse.
When enabled, interrupt will assert when
ADPG1_DET is set.
Table 5-10: HD and 3G Audio Core CSR Descriptions (Continued)
Addressh
Register Name
Parameter Name
Bit
R/W
Reset
Value
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com