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GS3471 Datasheet(PDF) 144 Page - Semtech Corporation |
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GS3471 Datasheet(HTML) 144 Page - Semtech Corporation |
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144 / 179 page ![]() GS3471 Final Data Sheet Rev.4 PDS-060498 September 2017 144 of 179 Semtech www.semtech.com A0B CFG_AUD_2 RSVD 15:12 — — Reserved. SEL_PHASE_SRC 11:11 RW 0 Selects between the Primary and Secondary embedded phase info when FORCE_PHASE_SRC set to 1. 0 = Use primary group phase information 1 = Use secondary group phase information FORCE_PHASE_SRC 10:10 RW 0 Phase source override: 0 = Auto phase source selection 1 = Manually set the phase source using SEL_PHASE_SRC RSVD 9:8 — — Reserved. FORCE_M 7:7 RW 0 Disables auto-detection of M value and forces it to the state specified by the FORCE_MEQ1001 signal. FORCE_MEQ1001 6:6 RW 0 Specifies M value when FORCE_M is set: 0 = M is 1.000 1 = M is 1.001 IGNORE_PHASE 5:5 RW 0 When HIGH, causes the HD_DEMUX to ignore the embedded clock info in both the Primary and Secondary group audio data packets. Clock is generated based on the video format and M value. FORCE_ACLK128 4:4 RW 0 When HIGH, causes the HD_DEMUX to ignore embedded clock info and derive phase information from ACLK128. EN_NOT_LOCKED 3:3 RW 0 Interrupt mask enable. When enabled, interrupt will assert when locked is not asserted. EN_NO_VIDEO 2:2 RW 0 Interrupt mask enable. When enabled, interrupt will assert when the video format is unknown. EN_INVALID_ EMBEDDED_ PHASE_B 1:1 RW 0 Interrupt mask enable for INVALID_EMBEDDED_PHASE_B. When enabled, interrupt will assert when INVALID_EMBEDDED_PHASE_B is set. EN_INVALID_ EMBEDDED_ PHASE_A 0:0 RW 0 Interrupt mask enable for INVALID_EMBEDDED_PHASE_A. When enabled, interrupt will assert when INVALID_EMBEDDED_PHASE_A is set. Table 5-10: HD and 3G Audio Core CSR Descriptions (Continued) Addressh Register Name Parameter Name Bit R/W Reset Value Description |
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