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AM5728 Datasheet(PDF) 164 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 164 Page - Texas Instruments

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AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Table 5-6. AVS and ABB Requirements per vdd_* Supply
SUPPLY
AVS REQUIRED?
ABB REQUIRED?
vdd_core
Yes, for all OPPs
No
vdd_mpu
Yes, for all OPPs
Yes, for all OPPs
vdd_ivahd
Yes, for all OPPs
Yes, for all OPPs
vdd_dspeve
Yes, for all OPPs
Yes, for all OPPs
vdd_gpu
Yes, for all OPPs
Yes, for all OPPs
vdd_rtc
No
No
5.5.2
Voltage And Core Clock Specifications
Table 5-7 shows the recommended OPP per voltage domain.
Table 5-7. Voltage Domains Operating Performance Points
DOMAIN
CONDITION
OPP_NOM
OPP_OD
OPP_HIGH
MIN
(2)
NOM (1) MAX (2)
MIN (2)
NOM (1) MAX (2)
MIN (2)
NOM (1)
MAX DC
(3)
MAX (2)
VD_CORE (V)
BOOT (Before AVS is
enabled) (4)
1.11
1.15
1.2
Not Applicable
Not Applicable
After AVS is enabled (4)
AVS
Voltag
e (5) –
3.5%
AVS
Voltage
(5)
1.2
Not Applicable
Not Applicable
VD_MPU (V)
BOOT (Before AVS is
enabled)(4)
1.06
1.15
1.2
Not Applicable
Not Applicable
After AVS is enabled(4)
AVS
Voltag
e (5) –
3.5%
AVS
Voltage
(5)
1.2
AVS
Voltage
(5) –
3.5%
AVS
Voltage
(5)
AVS
Voltage
(5) + 5%
AVS
Voltage
(5) –
3.5%
AVS
Voltage
(5)
AVS
Voltage
(5) +2%
AVS
Voltage
(5) + 5%
VD_RTC (V) (6)
-
0.84
0.88 to
1.06
1.16
Not Applicable
Not Applicable
Others (V)
BOOT (Before AVS is
enabled) (4)
1.02
1.06
1.16
Not Applicable
Not Applicable
After AVS is enabled(4)
AVS
Voltag
e (5) –
3.5%
AVS
Voltage
(5)
1.16
AVS
Voltage
(5) –
3.5%
AVS
Voltage
(5)
AVS
Voltage
(5) + 5%
AVS
Voltage
(5) –
3.5%
AVS
Voltage
(5)
AVS
Voltage
(5) +2%
AVS
Voltage
(5) + 5%
(1) In a typical implementation, the power supply should target the NOM voltage.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power on Hour). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power on Hour), and device power.
(5) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The
power supply should be adjustable over the following ranges for each required OPP:
–
OPP_NOM for MPU: 0.85 V – 1.15 V
–
OPP_NOM for CORE and Others: 0.85 V - 1.15 V
–
OPP_OD: 0.885 V - 1.15 V
–
OPP_HIGH: 0.95 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(6) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
(7) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM
boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.



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