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AM5728 Datasheet(PDF) 313 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 313 Page - Texas Instruments |
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313 / 415 page  313 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-80. GMAC RMII IOSETs SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX GMAC RMII1 RMII_MHZ_50_CLK U3 0 rmii1_txd1 V5 2 rmii1_txd0 V4 2 rmii1_rxd1 W9 2 rmii1_rxd0 V9 2 rmii1_rxer Y1 2 rmii1_txen U5 2 rmii1_crs V2 2 GMAC RMII0 RMII_MHZ_50_CLK U3 0 rmii0_txd1 Y2 1 rmii0_txd0 W2 1 rmii0_rxd1 V6 1 rmii0_rxd0 U6 1 rmii0_txen V3 1 rmii0_rxer U7 1 rmii0_crs V7 1 Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-81 Manual Functions Mapping for GMAC RMII0 for a definition of the Manual modes. Table 7-81 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-81. Manual Functions Mapping for GMAC RMII0 BALL BALL NAME GMAC_RMII0_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 0 1 U3 RMII_MHZ_50_CLK 0 0 CFG_RMII_MHZ_50_CLK_IN RMII_MHZ_50_CLK U6 rgmii0_txd0 500 500 CFG_RGMII0_TXD0_IN rmii0_rxd0 V6 rgmii0_txd1 840 1000 CFG_RGMII0_TXD1_IN rmii0_rxd1 U7 rgmii0_txd2 360 840 CFG_RGMII0_TXD2_IN rmii0_rxer V7 rgmii0_txd3 600 1000 CFG_RGMII0_TXD3_IN rmii0_crs Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-82 Manual Functions Mapping for GMAC RMII1 for a definition of the Manual modes. Table 7-82 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-82. Manual Functions Mapping for GMAC RMII1 BALL BALL NAME GMAC_RMII1_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 0 2 U3 RMII_MHZ_50_CLK 0 0 CFG_RMII_MHZ_50_CLK_IN RMII_MHZ_50_CLK V9 rgmii0_txctl 300 1000 CFG_RGMII0_TXCTL_IN rmii1_rxd0 |
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