 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM5728 Datasheet(PDF) 319 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM5728 Datasheet(HTML) 319 Page - Texas Instruments |
|
|
319 / 415 page  DSSD2 DSSD1 DSSD0 DSSD3 DSSD4 mmc1_clk mmc1_cmd mmc1_dat[3:0] vayu_mmc1_02 DSSD2 DSSD1 DSSD0 DSSD6 DSSD5 DSSD8 DSSD7 mmc1_clk mmc1_cmd mmc1_dat[3:0] vayu_mmc1_01 319 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-90. Timing Requirements for MMC1 - SD Card Default Speed Mode (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD8 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 20.46 ns Table 7-91. Switching Characteristics for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD0 fop(clk) Operating frequency, mmc1_clk 24 MHz DSSD1 tw(clkH) Pulse duration, mmc1_clk high 0.5*P- 0.185 (1) ns DSSD2 tw(clkL) Pulse duration, mmc1_clk low 0.5*P- 0.185 (1) ns DSSD3 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -14.93 14.93 ns DSSD4 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -14.93 14.93 ns (1) P = output mmc1_clk period in ns Figure 7-60. MMC/SD/SDIO in - Default Speed - Receiver Mode Figure 7-61. MMC/SD/SDIO in - Default Speed - Transmitter Mode 7.23.1.2 High speed, 4-bit data, SDR, half-cycle Table 7-92 and Table 7-93 present Timing requirements and Switching characteristics for MMC1 - High Speed in receiver and transmitter mode (see Figure 7-62 and Figure 7-63) Table 7-92. Timing Requirements for MMC1 - SD Card High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HSSD3 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.3 ns HSSD4 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.6 ns HSSD7 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.3 ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
