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AM5728 Datasheet(PDF) 323 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 323 Page - Texas Instruments |
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323 / 415 page  mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR501 SDR502L SDR502H SDR505 SDR506 SDR505 SDR506 vayu_mmc1_10 mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR508 SDR503 SDR507 SDR501 SDR502H SDR502L vayu_mmc1_09 SDR504 323 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-98. Timing Requirements for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR503 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 1.72 ns SDR504 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.6 ns SDR507 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 1.72 ns SDR508 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge Pad Loopbac k Clock 1.6 ns Internal Loopbac k Clock 1.6 ns Table 7-99. Switching Characteristics for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR501 fop(clk) Operating frequency, mmc1_clk 96 MHz SDR502 H tw(clkH) Pulse duration, mmc1_clk high 0.5*P- 0.185 (1) ns SDR502L tw(clkL) Pulse duration, mmc1_clk low 0.5*P- 0.185 (1) ns SDR505 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -3.66 1.46 ns SDR506 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -3.66 1.46 ns (1) P = output mmc1_clk period in ns Figure 7-68. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode Figure 7-69. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode 7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle Table 7-100 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 7-70 and Figure 7-71) |
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